component-basis roadmap

[FredericaBernkastel]

(might be updated)

• [x] logic gates (NOT, OR, AND, XOR, NAND, XNOR)
• [x] clock generators
• [x] one-pass
• [ ] signal router
  • [x] 1-2
  • [x] 1-4
  • [ ] 1-n (decade counter)
• [x] various flip-flop types (SR/JK latch)
• [x] phase sync
• [x] edge trigger
• [x] multiplexer
• [x] demultiplexer
  • [x] head splitter
• [x] serial half-adder
• [ ] serial half-subtractor
• [x] dynamic delay a programmable set of 2^n delays
• [x] time counter a time difference between CLK1 and CLK2, represented in uint
• [x] serial splitters (2^n)
• [x] ROM
  • [x] serial
  • [x] parallel
  • [x] segmented
  • [x] address decoder
• [ ] RAM
  • [ ] direct access
  • [ ] addressed access
  • [ ] stack
  • [ ] segmented
• [ ] binary encoder
• [x] binary decoder
• [ ] unary multiplier
• [ ] integral division
• [x] serial BIN > BCD
• [x] serial comparator compare two numbers without demultiplexing
• [x] serial pattern detector detect patterns in serial data without demultiplexing
• [ ] serial register (ring buffer) store data packet without demultiplexing
• [ ] shift registers
• [x] Rendez-vouz
• [ ] LUT
• [ ] LCPNG

---

• [x] 7-segment
• [x] parallel display interface
• [x] serial display interface
• [ ] keyboard input interface