Update the memory alignment within the Cortex-R5 port asm code

laroche commented 3 months ago

Update alignment in ARM_CR5 port.

This is the same patch as 553caa18ced4906cf5060823ada7a10e73c7b535 provided by Richard Barry for issue #426 (ARM_CA9).

Description

ARM_CA9 and ARM_CR5 are very close. This patch was applied to ARM_CA9, so it might also make sense to apply it to ARM_CR5.

This was just observed by looking at the changes between A9 and R5, no real testing was conducted.

[ ] I have tested my changes. No regression in existing tests.
[ ] I have modified and/or added unit-tests to cover the code changes in this Pull Request.

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

xuelix commented 3 months ago

Thanks for the PR, I am sending to the team for code review.

aggarg commented 2 months ago

so it might also make sense to apply it to ARM_CR5.

Did you face any problem or are you making these changes in anticipation of a problem?

laroche commented 2 months ago

This patch improves memory alignment for storing the floating point registers when switching between different tasks. This could be timing critical.

best regards,

Florian La Roche

aggarg commented 2 months ago

Thank you for explanation.

sonarcloud[bot] commented 2 months ago

Measures
0 Security Hotspots
No data about Coverage
No data about Duplication