Xilinx MPSoC R5F FreeRTOS TCP application

[LVS-AI]

It's unclear if the Zynq driver should be used for an R5F FreeRTOS TCP application on the Xilinx MPSoC because of the 32-bit nature of the cores. I wonder if possible to document a compatiability matrix for the various Xilinx hard and soft cores including MicroBlaze (original) and MicroBlaze-V (Risc-V) and the corresponding FreeRTOS TCP portable driver to use.

Application development around FreeRTOS TCP is greatly slowed when there are unknowns regarding the correct software components to pull together for a given hardware configuration. Expertise and knowledge sharing are key to building a larger FreeRTOS ecosystem.

[ActoryOu]

Hi @LVS-AI, We appreciate your insights on this matter. If you're open to it, we'd love to know if you'd be willing to contribute these valuable clarifications to the project. Alternatively, if you prefer, our team would be happy to assist in implementing these improvements. Would you be interested in contributing directly, or would you like us to help incorporate these changes?

Thank you.

[LVS-AI]

Hi @LVS-AI, We appreciate your insights on this matter. If you're open to it, we'd love to know if you'd be willing to contribute these valuable clarifications to the project. Alternatively, if you prefer, our team would be happy to assist in implementing these improvements. Would you be interested in contributing directly, or would you like us to help incorporate these changes?

Thank you.

Absolutely. I'm not savvy enough in the TCP realm so I look forward to learning alot on how the stack is put together from the subject matter experts (Amazon AWS etc.). I have a modest collection of Xilinx evaluation boards (VC707, ZC702, ZCU104) so testing coverage is reasonbly good going forward.

Who there can core dump their Xilinx knowledge on me so I can sort this all out into a nice tidy matrix? I'll need to be mentored/directed how best to proceed (roadmap).

[ActoryOu]

Hi @LVS-AI, The FreeRTOS-Plus-TCP repository includes support for different Xilinx platforms:

1. The xilinx_ultrascale directory contains support for Xilinx UltraScale+ devices, which use 64-bit Cortex-A53 processors.
2. The Zynq directory provides support for Xilinx Zynq devices.

If you're using a 32-bit processor of R5F, we recommend using the Zynq implementation.

To improve the clarity of this information for other users, we'd greatly appreciate your help in enhancing the documentation. Would you be willing to contribute by adding these details to the respective README files in each directory?

Thank you.

[LVS-AI]

My first thought is to express the matrix as a reworking of the repo directories. Something like ..

Xilinx

• Cortex-M
  • TEMAC
• MicroBlaze
  • TEMAC
• MicroBlaze-V
  • TEMAC
• MPSoC
  • A53
  • R5F
• Versal
  • MRMAC
• Zynq
  • A9

TEMAC driver(s) don't exist yet as far as we can tell. R5F driver is possibly the same as the Zynq A9 (not confirmed working).

In our particular use-case we want to serve-up certain AI acceleration (PL region) via a socket interface (micro-service) in a FreeRTOS TCP application. There is not a lot of documentation or samples to aid in this consolidation of knowledge.