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Dynamips development
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Dynagen reload issue with Dynamips 0.2.10-amd64 #30

Closed pstefanov closed 1 year ago

pstefanov commented 10 years ago

Hello,

I have noticed a bug when using dynagen with Dynamips 0.2.10-amd64 and trying to reload a router. Every time a router needs to be reloaded, I have to stop all the routers, exit dynagen, kill dynamips and start the dynamips and dynagen processes again. Please note that this is not due to lack of RAM - I have plenty available.

I get the following error messages:

In Dynagen:

=> reload R3

C7200 'R3': stopping simulation. 100-VM 'R3' stopped CPU0: carved JIT exec zone of 64 Mb into 2048 pages of 32 Kb. C7200 instance 'R3' (id 2): VM Status : 0 RAM size : 256 Mb IOMEM size : 256 Mb NVRAM size : 128 Kb NPE model : npe-400 Midplane : vxr IOS image : /opt/dynamips/images/c7200-advipservicesk9-mz.122-33.sre3.extracted.bin

Loading ELF file '/opt/dynamips/images/c7200-advipservicesk9-mz.122-33.sre3.extracted.bin'... ELF loading skipped, using a ghost RAM file. ELF entry point: 0x80008000

C7200 'R3': starting simulation (CPU0 PC=0xffffffffbfc00000), JIT enabled. 100-VM 'R3' started => MIPS64 Registers: zr ($ 0) = 0x0000000000000000 at ($ 1) = 0x0000000063de0000 v0 ($ 2) = 0x0000000000000000 v1 ($ 3) = 0x00000000630b0000 a0 ($ 4) = 0xffffffffffffffe8 a1 ($ 5) = 0x0000000000000001 a2 ($ 6) = 0x0000000000000000 a3 ($ 7) = 0x000000000000000e t0 ($ 8) = 0x0000000000000001 t1 ($ 9) = 0x0000000000000001 t2 ($10) = 0x000000006416a544 t3 ($11) = 0x000000006416a548 t4 ($12) = 0x000000006416a530 t5 ($13) = 0x00000000000003fc t6 ($14) = 0x00000000000000ff t7 ($15) = 0x000000006416a4f4 s0 ($16) = 0x000000006416a094 s1 ($17) = 0x0000000061720f28 s2 ($18) = 0x0000000063b4502c s3 ($19) = 0x000000006416a08c

MIPS64 Registers: zr ($ 0) = 0x0000000000000000 at ($ 1) = 0x0000000064070000 v0 ($ 2) = 0x0000000000000000 v1 ($ 3) = 0x0000000000000000 a0 ($ 4) = 0x0000000000000038 a1 ($ 5) = 0x000000007cffffa8 a2 ($ 6) = 0x0000000064170000 a3 ($ 7) = 0x0000000000000001 t0 ($ 8) = 0x0000000000000020 t1 ($ 9) = 0x0000000000000038 t2 ($10) = 0x0000000000000000 t3 ($11) = 0x0000000000000038 t4 ($12) = 0x0000000000008000 t5 ($13) = 0xffffffffffff00ff t6 ($14) = 0x0000000000000000 t7 ($15) = 0x0000000000000000 s0 ($16) = 0x0000000000000000 s1 ($17) = 0x0000000061747474 s2 ($18) = 0x0000000063b40000 s3 ($19) = 0x0000000000000001 s4 ($20) = 0x0000000063b40000 s5 ($21) = 0x00000000637e0000 s6 ($22) = 0x000000000000000d s7 ($23) = 0x0000000000000012 t8 ($24) = 0x0000000000000000 t9 ($25) = 0x00000000617a364c k0 ($26) = 0x00000000642d2e60 k1 ($27) = 0x0000000000000000 gp ($28) = 0x0000000063ded340 sp ($29) = 0x0000000063dcf618 fp ($30) = 0x0000000000000034 ra ($31) = 0x000000006177c54c lo = 0x0000000000001040, hi = 0x0000000000000000 pc = 0x000000006177c580, ll_bit = 0 Instruction: 8c680040 lw t0,64(v1)

CP0 Registers: index ($ 0) = 0x0000000000000005 random ($ 1) = 0x0000000000000012 entry_lo0 ($ 2) = 0x0000000001200017 entry_lo1 ($ 3) = 0x0000000001210017 context ($ 4) = 0x0000000000000000 pagemask ($ 5) = 0x00000000007fe000 wired ($ 6) = 0x0000000000000000 info ($ 7) = 0x0000000020000000 badvaddr ($ 8) = 0x000000000000001c count ($ 9) = 0x0000000040c6b40e entry_hi ($10) = 0x000000003c000000 compare ($11) = 0x0000000040cb3aa6 status ($12) = 0x0000000034008001 cause ($13) = 0x000000000000000c epc ($14) = 0x0000000061747474 prid ($15) = 0x0000000000002721 config ($16) = 0x0000000000c08ff0 ll_addr ($17) = 0x0000000000000000 watch_lo ($18) = 0x0000000000000000 watch_hi ($19) = 0x0000000000000000 xcontext ($20) = 0x0000000000000000 cp0_r21 ($21) = 0x0000000000000000 cp0_r22 ($22) = 0x0000000000000000 cp0_r23 ($23) = 0x0000000000000000 cp0_r24 ($24) = 0x0000000000000000 cp0_r25 ($25) = 0x0000000000000000 ecc ($26) = 0x0000000000000000 cache_err ($27) = 0x0000000000000000 tag_lo ($28) = 0x0000000000000000 tag_hi ($29) = 0x0000000000000000 err_epc ($30) = 0x0000000000000000 cp0_r31 ($31) = 0x0000000000000000

IRQ count: 2955, IRQ false positives: 21, IRQ Pending: 0 Timer IRQ count: 2535, pending: 25, timer drift: 0

Device access count: 197824

MIPS64 Registers: zr ($ 0) = 0x0000000000000000 at ($ 1) = 0x0000000063de0000 v0 ($ 2) = 0x0000000000000001 v1 ($ 3) = 0x000000007cffffb8 a0 ($ 4) = 0x0000000000000000 a1 ($ 5) = 0x000000007bffff60 a2 ($ 6) = 0x0000000000000001 a3 ($ 7) = 0x00000000637e0000 t0 ($ 8) = 0xffffffffffffffff t1 ($ 9) = 0x0000000063de0000 t2 ($10) = 0x00000000630b3620 t3 ($11) = 0x00000000630b0000 t4 ($12) = 0x0000000000000000 t5 ($13) = 0x0000000000000001 t6 ($14) = 0x0000000000000000 t7 ($15) = 0x0000000000000002 s0 ($16) = 0x0000000000000000 s1 ($17) = 0x0000000061720f28 s2 ($18) = 0x000000006416a094 s3 ($19) = 0x0000000000000000 s4 ($20) = 0x000000006416a08c s5 ($21) = 0x000000007bffff50 s6 ($22) = 0xffffffffffffffe8 s7 ($23) = 0x0000000061782de0 t8 ($24) = 0x0000000000000000 t9 ($25) = 0x0000000000000000 k0 ($26) = 0xffffffffbfc003e0 k1 ($27) = 0x0000000000008000 gp ($28) = 0x0000000063ded340 sp ($29) = 0x0000000065b03e40 fp ($30) = 0x0000000064366a70 ra ($31) = 0x0000000061746c58 lo = 0x0000000000001040, hi = 0x0000000000000000 pc = 0x0000000061746c78, ll_bit = 0 Instruction: ae6a000c sw t2,12(s3)

CP0 Registers: index ($ 0) = 0x0000000000000005 random ($ 1) = 0x0000000000000003 entry_lo0 ($ 2) = 0x0000000001200017 entry_lo1 ($ 3) = 0x0000000001210017 context ($ 4) = 0x0000000000000000 pagemask ($ 5) = 0x00000000007fe000 wired ($ 6) = 0x0000000000000000 info ($ 7) = 0x0000000020000000 badvaddr ($ 8) = 0x0000000000000040 count ($ 9) = 0x000000004262aa92 entry_hi ($10) = 0x000000003c000000 compare ($11) = 0x0000000042673766 status ($12) = 0x000000003400ff01 cause ($13) = 0x0000000000000000 epc ($14) = 0x0000000061782738 prid ($15) = 0x0000000000002721 config ($16) = 0x0000000000c08ff0 ll_addr ($17) = 0x0000000000000000 watch_lo ($18) = 0x0000000000000000 watch_hi ($19) = 0x0000000000000000 xcontext ($20) = 0x0000000000000000 cp0_r21 ($21) = 0x0000000000000000 cp0_r22 ($22) = 0x0000000000000000 cp0_r23 ($23) = 0x0000000000000000 cp0_r24 ($24) = 0x0000000063db0000 cp0_r25 ($25) = 0x0000000000000000 ecc ($26) = 0x0000000000000000 cache_err ($27) = 0x0000000000000000 tag_lo ($28) = 0x0000000000000000 tag_hi ($29) = 0x0000000000000000 err_epc ($30) = 0x0000000000000000 cp0_r31 ($31) = 0x0000000000000000

IRQ count: 3050, IRQ false positives: 21, IRQ Pending: 0 Timer IRQ count: 2625, pending: 5, timer drift: 0

Device access count: 276702

% No memory map for code execution at 0xdfb10088dfb20000 % Unable to create instruction block for vaddr=0xdfb10088dfb20000 insn_page_compile: unable to create JIT block. VM 'R3': unable to compile block for CPU0 PC=0xdfb10088dfb20090

On the device:

-Traceback= $0 : 00000000, AT : 64070000, v0 : 00000000, v1 : 00000000 a0 : 00000038, a1 : 7CFFFFA8, a2 : 64170000, a3 : 00000001 t0 : 00000020, t1 : 00000038, t2 : 00000000, t3 : 00000038 t4 : 00008000, t5 : FFFF00FF, t6 : 00000000, t7 : 00000000 s0 : 00000000, s1 : 61747474, s2 : 63B40000, s3 : 00000001 s4 : 63B40000, s5 : 637E0000, s6 : 0000000D, s7 : 00000012 t8 : 00000000, t9 : 617A364C, k0 : 642D2E60, k1 : 00000000 gp : 63DED340, sp : 63DCF618, s8 : 00000034, ra : 6177C54C EPC : 6177C580, ErrorEPC : 00000000, SREG : 34008003 MDLO : 00001040, MDHI : 00000000, BadVaddr : 00000040 CacheErr : 00000000, DErrAddr0 : 00000000, DErrAddr1 : 00000000 DATA_START : 0x62AFA000 Cause 00000008 (Code 0x2): TLB (load or instruction fetch) exception

-Traceback=

%ALIGN-1-FATAL: Corrupted program counter 01:26:01 UTC Thu Mar 6 2014 pc=0x61746C78 , ra=0x61746C58 , sp=0x65B03E40

%ALIGN-1-FATAL: Corrupted program counter 01:26:01 UTC Thu Mar 6 2014 pc=0x61746C78 , ra=0x61746C58 , sp=0x65B03E40

01:26:01 UTC Thu Mar 6 2014: TLB (store) exception, CPU signal 10, PC = 0x61746C78

Possible software fault. Upon recurrence, please collect

crashinfo, "show tech" and contact Cisco Technical Support.

-Traceback= $0 : 00000000, AT : 63DE0000, v0 : 00000001, v1 : 7CFFFFB8 a0 : 00000000, a1 : 7BFFFF60, a2 : 00000001, a3 : 637E0000 t0 : FFFFFFFF, t1 : 63DE0000, t2 : 630B3620, t3 : 630B0000 t4 : 00000000, t5 : 00000001, t6 : 00000000, t7 : 00000002 s0 : 00000000, s1 : 61720F28, s2 : 6416A094, s3 : 00000000 s4 : 6416A08C, s5 : 7BFFFF50, s6 : FFFFFFE8, s7 : 61782DE0 t8 : 00000000, t9 : 00000000, k0 : BFC003E0, k1 : 00008000 gp : 63DED340, sp : 65B03E40, s8 : 64366A70, ra : 61746C58 EPC : 61746C78, ErrorEPC : 00000000, SREG : 3400FF03 MDLO : 00001040, MDHI : 00000000, BadVaddr : 0000000C CacheErr : 00000000, DErrAddr0 : 00000000, DErrAddr1 : 00000000 DATA_START : 0x62AFA000 Cause 0000000C (Code 0x3): TLB (store) exception

=== Flushing messages (01:26:01 UTC Thu Mar 6 2014) ===

Buffered messages: Queued messages: No cache error exceptions since boot

No warm reboot Storage

LocutusOfBorg commented 10 years ago

:100: I have this bug since I started using it.

flaviojs commented 10 years ago

Thank you for reporting. =) Unfortunately, the reload mechanism involves the microcode, which we're missing the source. So don't expect any progress until after issue #7 is closed.

As a side note, do you know of any hardware+image combination that has reload working?