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GadgetFactory / DesignLab

FPGA Soft Processor IDE - Use Arduino Sketches and a schematic editor to make custom SOC designs for Papilo FPGA's.
http://www.papillio.cc/
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DesignLab overwrites library assignments on every opening of a project #27

Closed smuehlst closed 1 year ago

smuehlst commented 9 years ago

In this thread Jack helped me out to find the cause why the ISim simulation of a simple design did not work. The fix was to move DesignLab library files in ISE from the "DesignLab" library folder into the "work" folder.

The problem is that DesignLab rewrites the library assignments when the project is opened again in DesignLab. So after a project has been fixed in ISE for running an ISim simulation, after closing the design in ISE and closing the sketch in DesignLab, and after reopening the sketch in DesignLab and reopening the design in ISE, the simulation is broken again,