Closed dhand-galois closed 4 years ago
Some stats:
Test | Actual FPGA Freq | Tracing Support | Simulated Freq | Debian Boot (sec) |
---|---|---|---|---|
Test 1 | 100MHz | Yes - end=-1 |
39-40MHz | 351 |
Test 2 | 100MHz | No | 61.33MHz | 229 |
Test 3 | 75MHz | No | 48.14MHz | 286 |
Test 4 | 100MHz | Yes - end=1 |
59.85MHz | 231 |
Roughly 50% speedup.
How does this get packaged into final FireSim builds of GFE and LMCO's and UMich's processors?
This has been merged into the build flow as of #105 and into FETT-Target as of https://github.com/DARPA-SSITH-Demonstrators/SSITH-FETT-Target/commit/f5a31db05599e7999cee5098fb7093a1dce1321e. All of the stand-alone FireSim swpkgs on S3 have also been updated to include this fix. So closing this as complete.
Despite what is claimed in the documentation, adding trace support to FireSim builds can decrease simulation performance even when not saving the trace to a file. The trace data is still transferred over the host connection and then ignored.
Thankfully, there is a simple solution - the trace start and end cycles are configured into the FPGA-side bridge component at runtime. Setting
+trace-end0=1
instead of+trace-end0=-1
achieves nearly the same performance as an AFI built without tracing support (within 1-2 effective MHz).This issue will track updating the swpkg scripts for each processor to include this change.