AWSteria GFE Step 2: Same as Step 1, but with Verilator/Bluesim flow enabling more convenient development

[rsnikhil]

Same functionality as Step 1, i.e., BSV P2+DDR4; DMA program load; ISA tests. This replaces the IP from AWS-FPGA XSIM (specifically: BFM (Bus Functional Model) and encrypted ddr4 models) with BSV versions so development can proceed independently, and (hopefully) much faster builds and simulation. Note: AWS-FPGA XSIM flow cannot be simply compiled for verilator/Bluesim because of encrypted IP, non-synthesizable SV in the BFM, etc. We will maintain this flow in parallel with the standard AWS XSIM flow.

[kiniry]

Please add CharlieH to the assignees of any of these issues if he is performing on them.

[rsnikhil]

Priority lowered per input from Cambridge, in favor of other tasks: work out FPGA flow, OS bringup

[kiniry]

Do you expect to work on this and possibly complete it in the current sprint @rsnikhil ? If not, please move it to the backlog and remove the milestone. I'm optimistically moving it to Sprint 3 based upon our discussion today.

[rsnikhil]

Bluesim AWSteria has just now successfully run the same host-side-C + FPGA-side_BSV example that we've been using in the standard AWS XSIM flow and FPGA-flow (DCP->AFI). Specifically:

• Exercise DMA (AXI4 DMA PCIS interface) to each of the 4 DDRs; read-back using DMA and cross-check
• Use DMA (AXI4 DMA PCIS interface) to download a Mem.hex file for an ISA test; read-back using DMA and cross-check
• Use peek/poke (AXI4 Lite OCL interface) to allow Flute to execute the ISA test, and collect final ISA test success/fail status

Verilator imports C somewhat differently from Bluesim (for comms with host-side C). The solution is known (and we've done it before many times), so we expect Verilator AWS to follow shortly.

All this needs some cleanup and documentation, and then I will close this issue.

[rsnikhil]

Bluesim integration is ready, just awaiting a small fix in the U.Cambridge AXI4-Lite transactors (see note in Issue #66). Verilator integration still pending.

[rsnikhil]

Closing this issue now, since Bluesim flow has stabilized and been used a bit. Verilator flow is pending, but not high priority since Bluesim flow is working (Verilator flow may increase simulation speed a bit, that's the only advantage). We're not abandoning Verilator flow, just putting it off for opportunistic completion when we find a moment (only a small issue remains, to get it working).