gr: rename gf100_gr_waitidle for gk104* …
The status bit used in gf100_gr_wait_idle only exists starting gk104.
As the function is currently used in gk20a and later, rename the function
to use gk104 prefix to reflex correct supported chip version.
Signed-off-by: Xia Yang xiay@nvidia.com
Fix the channel id bit mask in FIFO schedule timeout error handling.
FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff.
gr: rename gf100_gr_waitidle for gk104* … The status bit used in gf100_gr_wait_idle only exists starting gk104. As the function is currently used in gk20a and later, rename the function to use gk104 prefix to reflex correct supported chip version.
Signed-off-by: Xia Yang xiay@nvidia.com
Fix the channel id bit mask in FIFO schedule timeout error handling.
FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff.
Signed-off-by: Xia Yang xiay@nvidia.com