Brainstorm ISA

[GrapesGoober]

Redesign - here

The register file introduces nasty problems regarding multiplexer circuit arrangements, spaghetti IC basic-blocks, and poopy register allocation. Redesigning Simplic to use a accumulator-based simplifies IC compiling.

FYI - booleans

Note that boolean variables are essentially "zero" or "not zero" integers.

Current candidate Opcodes

ACC MEM BSP JMP - Control SFT CLZ ADD SUB - Common Arithmatic MUL LML DIV MOD - Arithmatic BOL AND ORR NOT - Logic Instructions

Dedicated flag-to-variable instruction

If we were to store a comparison as a boolean variable, we'd need to use branching, accumulator-set, then store onto variable. This could verbosify the boolean expressions somewhat. What about a dedicated instruction with cond4 to store flag results onto accumulator?

The idea is that we have one instruction that either set 1 or 0 onto accumulator (remember, we only have true/false here) which can then be stored.

Control Bits - Cond4

The control bits will be devided into mode2 and flag2. Mode 2 is one problem. Let's talk about flag2.

Mode2 Offset1 Flag1

• Mode: specify how the instruction executes
• Offset: specify whether to offset from BSP or P
• Flag: specify whether to update flag or ignore

This can be interesting, but the mode2 makes me uneasy. Say, for arithmatic instructions, there could be 1 bit for immediate as-is/addressing and another for carry (as in add and sub), or sign (as in mul, lml, div, mod)

[GrapesGoober]

Preferred

Hex	Opcode	c1	c2	c3	c4
0	INS	a/p
1	LD	a/p
2	ST
3	JMP	c1	c2	c3	c4
4	BSP	c/r
5	CLZ
6	SFT		i	s1	s2
7	ADD	c	i	b/p	f
8	SUB	c	i	b/p	f
9	MUL	s	i	b/p	f
A	LML	s	i	b/p	f
B	DIV	s	i	b/p	f
C	MOD	s	i	b/p	f
D	AND		i	b/p	f
E	OR		i	b/p	f
F	NOT	n	i	b/p	f

[GrapesGoober]

FYI modified ISA > reducing instructions by expanding mode bits

#	opcode	mode2	flag2	description
0	INS	A/P set/ins	- -
1	MEM	A/P OP1	- ZN	mem[P+Imm8]
2
3	JMP	cond4	cond4	PC = mem[P+Imm8]
4	BSP	call/ret -	- -	P = P +- Imm8
5
6	CLZ	- -	- Z
7	SFT	OP2	- ZN	A << mem[P+Imm8]
8
9	ADD	i -	CV ZN
A	SUB	i -	CV ZN
B	MUL	LMUL -	- ZN
C	DIV	MOD -	- ZN
D	AND	- -	- ZN
E	ORR	- -	- ZN
F	NOT	NEG -	- ZN	Can do 2-comp

[GrapesGoober]

FYI ISA 3 - Mode2 With Imm10, no third register

opcode	mnemonic	mode	note
0	jump		cond4 is in imm
1	load	ins/push bsp/B
2	store	idx1 bsp/A
3	ins	bspAdd/bspSub/sPush/sIns
4	sft	op2	shift with value
5	sfti	op2	shift immediate
6	clz
7	add	idx1 c
8	sub	idx1 c
9	mul	idx2

A B|div| idx2 C D|and| idx1 E|or| idx1 F|nor| idx1

Problems

• Does not require third register [c]
• But the jump instruction needs to be preceded by a compare (subtract) instruction
• Solutions?
  • Separate jump instructions? Mode? one for immediate, one for internally compare, one for precompared
  • internally compare is finicky, since it requires A and B, but also branching address as well
  • Instead, flag/ImmEq/ImmNotEq/ImmLess might seem more practical, but too specialized

[GrapesGoober]

FYI ISA 4 - Mode2 With Imm10, no third register

opcode	mnemonic	mode	note
0	jump		cond4 is in imm
1	load	ins/push bsp/B
2	store	idx1 bsp/A
3	ins	bspAdd/bspSub/sPush/sIns

4 5 6|sft|op2| shift with value 7|sfti|op2| shift immediate 8|clz 9|add| idx1 c A|sub| idx1 c B|mul| idx2 C|div| idx2 D|and| idx1 E|or| idx1 F|nor| idx1

Problems

• SFT instruction still requires idx1, but is instead replaced by op2
  • Solution? dedicated store for sft?
• The jump instruction needs to be preceded by a compare (subtract) instruction
• Solutions?
  • Separate jump instructions? Mode? one for immediate, one for internally compare, one for precompared
  • internally compare is finicky, since it requires A and B, but also branching address as well
  • Instead, flag/ImmEq/ImmNotEq/ImmLess might seem more practical, but too specialized

[GrapesGoober]

Preferred

FYI ISA 5 - Mode2, Imm10, Using 16-bit word for the RAM

opcode	name	mode	notes
0	ins	A/B set
1	bsp	call/return	can only add/sub
2	load	A/B bsp/A	can load from heap
3	store	A/B bsp/A	can store both stack and heap
4	jump	set/add/sub
5
6
7	clz
8	sft	op2
9	add	c
A	sub	c
B	mul	lmul
C	div	mod
D	and
E	or
F	not

Notes

• accumulator A addressing mode is done via shift-left (insert-like) and not to "add" (unlike bsp-offset). For example, to load 0x1460 from heap, we need to first insert to A with the first 6 msb bits ins A 0x1 then load 0x460.

Improvement Ideas

Mode4 and Imm8

Working with imm8 as opposed to imm10 might be easier. Having mode4 might be hard to fulfill

• imm8 can have a potential to be quite limiting, although 256 variables in only a single function does not seem too bad. 1024 variables, on the other hand, is a tad bit too much
• mode4 also allows for cond4 as well. Note that using imm8 for jump instructions isn't ideal. It might actually be easier to implement local branches (non-call branches) using address anyways. Furthermore only 256 is a little limiting for branches, so it shall be proceeded with one ins-A-8-bits first. Keep in mind that using imm10 would still require the insert instruction.
• extra "mode" bit has the potential to allow the ALU instructions write directly to heap. However, since we only have 2 accumulators A and B, we have no way to store the address.
  • one way is for heap memory be an in-situ operation. for example, mem[a] += b.
  • another option is to have >1 accumulators. Maybe have A and B, but another "Pointer" register. With some spare extra mode bits, the insert instruction now has A/B/P. Note that P is only needed to be 8 bits since the load/ALU already has imm8 (so no insert for P, just set).

Complex unsigned extender requires add/sub mode bit. This adds to mux complexity.

• Solutions? remove add/sub feature, and allow for only sign extender?
• Useless for bsp-offsets, since there's no need to read values from the caller function
• Useful for bsp, since it allows for call/return (i.e. add or subtract)

Potential new instructions?

• separate jump instructions, we have add/sub (for loop) and set (for function calls)

[GrapesGoober]

FYI ISA 6 - Mode4, Imm8

There's so much opportunity for mode4, but I don't know what to include

opcode	name	#m-bits	mode	notes
0	ins	3	A/B/P set/ins
1	bsp	1	call/return	can only add/sub
2	load	3	A/B/P bsp/P	can load from heap
3
4	jump	4	cond4
5
6
7	clz	1	bsp/P
8	sft	3	op2 bsp/P
9	add	2	c bsp/P
A	sub	2	c bsp/P
B	mul	2	lmul bsp/P
C	div	2	mod bsp/P
D	and	1	bsp/P
E	or	1	bsp/P
F	not	1	bsp/P

[GrapesGoober]

Preferred

FYI ISA 7, mode4, imm8

#	opcode	mode4	description
0	INS	A/P set/ins - -
1	LDA	A/P - - ZN
2	STA	A/P - - ZN
3	JMP	cond4	PC = mem[P+Imm8]
4
5
6
7	CLZ	- - - Z
8	SFT	OP2 - ZN
9	ADD	- - C ZNV
A	SUB	- - C ZNV
B	MUL	LMUL - C ZN
C	DIV	MOD - C ZN
D	AND	- - - ZN
E	ORR	- - - ZN
F	NOT	- - - ZN

Notes

• This introduces flag bits into the mode4. This shrinks down to imm8.
• Not all bits in the mode4 are being used, but that's OK. The important part is that those bits are consistant, which makes the circuitry much simpler.
• However, it still makes for some slight complexity. Some instructions does not allow C flag, or V flag, (as using those flags might cause undefined behaviour). As such, those flags must be clear. This might be a little complex to implement.

[GrapesGoober]

Moved to "finalize ISA"