Closed wangliwei-intel closed 2 years ago
There is no explicit multicore support.
However the bus used can support multiple hosts (already 2 are used, one for Ibex the other for the debug module). So it would be possible to instantiate multiple Ibex cores and hook them all up to the same memory and peripheral set.
There is no explicit support for coherency or other multi-core features. Ibex has no data cache so you may not need any depending upon your use case.
You would probably want to improve the bus to get better performance.
@GregAC Thanks for your quick and informative answer.
Yes, I agree with you, without cache and coherency, the idea looks not right. Somehow, I got this wrong idea.
B. R.
Does it support multicore?