Open snematbakhsh opened 2 years ago
Right now there's out of the box way to change the Ibex configuration. It would be possible to expose these parameters at the FPGA top level (top_artya7.sv) and then fuseSoC could set them. This would be a worthwhile future enhancement to super system.
In the mean time I'd suggest setting parameters within ibex_super_system.sv
where ibex_top
is instantiated however your method also works fine. In general you shouldn't alter the files within the vendor/ directory but practically this is only a issue when you come to bring in a new version of Ibex. As your changes will be trivial it shouldn't be hard to reapply them if you do vendor in a newer version of Ibex.
Leaving this issue open as a reminder to me to do the enhancement described in my previous comment.
Thanks for the info. Is df5b88d5ed5d19f1757bfad9f04c6e451404e671 similar to what you had in mind? Happy to submit a PR if so.
Instead of the fixed config structures selected by a single string parameter I'd expose all of the parameters in the ibex_super_system/top_artya_a7 top-level then the build system can provide the various configuration sets. If you look in the Ibex repository we have a YAML file that defines various configurations.
If there a convenient way to change the Ibex core configuration parameters for synthesis (for example, to change the multiplier implementation to RV32MSingleCycle)? I experimented a bit with the build options and I didn't find a way to set those parameters externally in a way that Vivado would respect. Of course changing the parameters directly in the rtl works fine, e.g.:
... but is there a better way to do it? Sorry for the beginner question, I am a newbie with Vivado and related tools.