JTAG interface

[aviator00]

I want to test the project on a ZedBoard. How can work if the JTAG signals are all 0? where is defined DMIDirectTAP? How can I modify the code making JTAG external?

[GregAC]

Currently it uses the Xilinx BSCANE2 primitive, see https://github.com/GregAC/ibex_super_system/blob/main/vendor/pulp_riscv_dbg/src/dmi_bscane_tap.sv

To use an external JTAG probe you need to switch to using the normal JTAG tap (https://github.com/GregAC/ibex_super_system/blob/main/vendor/pulp_riscv_dbg/src/dmi_jtag_tap.sv). To do this alter the https://github.com/GregAC/ibex_super_system/blob/main/pulp_riscv_dbg.core fusesoc core file to use dmi_jtag_tap.sv rather than dmi_bscane_tap.sv.

This is the line to alter:

https://github.com/GregAC/ibex_super_system/blob/3ae1363990828a88350cd2641681dfb6d706954c/pulp_riscv_dbg.core#L22

Then the TAP instantiation in dm_top:

https://github.com/GregAC/ibex_super_system/blob/3ae1363990828a88350cd2641681dfb6d706954c/rtl/system/dm_top.sv#L235-L258

needs it's JTAG signals wiring out to the top level so they can be connected up appropriately (don't forget synchronizers for external inputs).

I don't think DMIDirectTAP is defined anywhere. It's just a left over bit of code as I copied the DM setup out of OpenTitan.

[aviator00]

Thank you, very clear. I tried successfully with Xilinx BSCANE2 primitive present also on the Zedboard at the moment, because it's easier, copying some openocd configurations from others.