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Gripnook / digital-storage-oscilloscope

An FPGA implementation of a digital storage oscilloscope.
MIT License
24 stars 6 forks source link

Change clock rate to 40MHz #13

Closed Gripnook closed 7 years ago

Gripnook commented 7 years ago

This will make interfacing with the ADC simpler.

Gripnook commented 7 years ago

Better to let only the ADC run at 40MHz and have a clock interface.

Gripnook commented 7 years ago

Duplicate of ADC configuration.