Frequency range

[Rihab86]

I tried to use your project and make some modifications in order to measure the frequency of an ADC signal input which goes from 1Mhz to 100MHz. How can I proceed ? What is the utility of using the clock domain crossing fifo ?

[Gripnook]

To measure a 100 MHz signal accurately, you will need an ADC with at least 200 MSa/s, preferably 250 MSa/s, in order to properly interpolate it. You will also need an FPGA with a higher clock speed than the one I used (50 MHz) to properly work with such an ADC. If you actually need to measure a signal of that high frequency, you might be better off using a commercially available oscilloscope instead.

More information on sampling and interpolation can be found in this Agilent paper. https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/research/Sin(x)x_Agilent.pdf

The FIFO queue is described in section F of the report. It serves to decouple the ADC output from the rest of the circuit since they run at different clock rates. https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/report/final-report/final-report.pdf

[Rihab86]

Hello sir,

I already have a daughter board with an ADC working on 250Msps and I need to estimate the frequency of the input signal because I have to make some signal processing depending on which frequency i Heard.

Le lun. 15 juin 2020 à 17:36, Andrei Purcarus notifications@github.com a écrit :

To measure a 100 MHz signal accurately, you will need an ADC with at least 200 MSa/s, preferably 250 MSa/s, in order to properly interpolate it. You will also need an FPGA with a higher clock speed than the one I used (50 MHz) to properly work with such an ADC. If you actually need to measure a signal of that high frequency, you might be better off using a commercially available oscilloscope instead.

More information on sampling and interpolation can be found in this Agilent paper.

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/research/Sin(x)x_Agilent.pdf

The FIFO queue is described in section F of the report. It serves to decouple the ADC output from the rest of the circuit since they run at different clock rates.

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/report/final-report/final-report.pdf

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/Gripnook/digital-storage-oscilloscope/issues/16#issuecomment-644209228, or unsubscribe https://github.com/notifications/unsubscribe-auth/AGWVF7L5OBBSIPVOQVKEO4TRWY5XNANCNFSM4N55PLYQ .

[Gripnook]

Do you have an FPGA? If so, you need to work with the associated software to compile and run the HDL and upload it to the device.

You'll need to instantiate the top level components and link the ports to the correct FPGA ports, and you might need to implement the ADC protocol for data acquisition and feed that into the oscilloscope if your ADC uses a different protocol to the one for the DE1-SoC board. https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/src/oscilloscope.vhd https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/src/digital_storage_oscilloscope.vhd https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/datasheets/DE1-SoC_User_manual_ref.pdf

[Rihab86]

Hello Sir,

I have already done thiese steps and your project works but only using your parameters, i.e until 200KHz of signal frequency and I want it to be until 100Mhz ;)

Le lun. 15 juin 2020 à 22:59, Andrei Purcarus notifications@github.com a écrit :

Do you have an FPGA? If so, you need to work with the associated software to compile and run the HDL and upload it to the device.

You'll need to instantiate the top level components and link the ports to the correct FPGA ports, and you might need to implement the ADC protocol for data acquisition and feed that into the oscilloscope if your ADC uses a different protocol to the one for the DE1-SoC board.

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/src/oscilloscope.vhd

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/src/digital_storage_oscilloscope.vhd

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/datasheets/DE1-SoC_User_manual_ref.pdf

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/Gripnook/digital-storage-oscilloscope/issues/16#issuecomment-644386220, or unsubscribe https://github.com/notifications/unsubscribe-auth/AGWVF7JX6VBSY6Y4FG4BAQDRW2DTFANCNFSM4N55PLYQ .

-- -- Rihab HMIDA

MC2 Technologies10 Rue Hubble, 59262 Sainghin-en-Mélantois rihab.hmida@mc2-technologies.com

[Rihab86]

I tried to modify the samplerate but the FFT is not as clean as with 0.5Mhz of clocking.

Le mar. 16 juin 2020 à 09:24, hmida rihab hmida.rihab@gmail.com a écrit :

Hello Sir,

I have already done thiese steps and your project works but only using your parameters, i.e until 200KHz of signal frequency and I want it to be until 100Mhz ;)

Le lun. 15 juin 2020 à 22:59, Andrei Purcarus notifications@github.com a écrit :

Do you have an FPGA? If so, you need to work with the associated software to compile and run the HDL and upload it to the device.

You'll need to instantiate the top level components and link the ports to the correct FPGA ports, and you might need to implement the ADC protocol for data acquisition and feed that into the oscilloscope if your ADC uses a different protocol to the one for the DE1-SoC board.

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/src/oscilloscope.vhd

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/src/digital_storage_oscilloscope.vhd

https://github.com/Gripnook/digital-storage-oscilloscope/blob/master/datasheets/DE1-SoC_User_manual_ref.pdf

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/Gripnook/digital-storage-oscilloscope/issues/16#issuecomment-644386220, or unsubscribe https://github.com/notifications/unsubscribe-auth/AGWVF7JX6VBSY6Y4FG4BAQDRW2DTFANCNFSM4N55PLYQ .

--

Rihab HMIDA

MC2 Technologies10 Rue Hubble, 59262 Sainghin-en-Mélantois rihab.hmida@mc2-technologies.com

-- -- Rihab HMIDA

MC2 Technologies10 Rue Hubble, 59262 Sainghin-en-Mélantois rihab.hmida@mc2-technologies.com

[Gripnook]

I'm going to need more information. What isn't working? What FFT is not as clean?

• Are you unable to scale the VGA output to display data in your desired frequency range?
• Are you able to get the VGA output to work, but higher frequency signals don't look right?

[Gripnook]

After re-reading bits of my paper (it's been a long time), I realized the VGA signal was based on a 50 MHz clock. If you're using a higher clock rate you might need to reduce it for the VGA driver.

http://tinyvga.com/vga-timing

[Rihab86]

The VGA works right. It works on 50MHz. I only try to modify the sample_rate of the FFT to have more FFT range on my screen. For a sample rate of 5Mhz, the FFT range is 5MHz/4=1.25MHz. I want to display 100MHz of FFT range, it means that I should put the sample_rate on 400MHz. I do so, but I do have anything on my screen, only some noise.

[Gripnook]

What FFT are you referring to?