Closed GustawKubala closed 1 year ago
Discuss how likely it is that we will need the clock descaler and if it's easier to translate the one we have to do in VHDL for our PSC lab classes to Verilog compared to translating what we already have to VHDL
We made a descaler as part of our PSC classes.
Discuss how likely it is that we will need the clock descaler and if it's easier to translate the one we have to do in VHDL for our PSC lab classes to Verilog compared to translating what we already have to VHDL