Open campbellsan opened 11 years ago
192 kHz is no problem with my I2S driver. You have to "modify" the board in a sense that you have to wire the P5 signals.
I never got to routing a board for the J5 signals.
You can bring the J5 pins onto the Guzunty I/O in any way that is convenient for you.
Final note here... the AL1402 outputs are not strictly I2S - they do not have the 1-bit clock delay of I2S. Can the I2S Pi driver be configured to read MSB as the first bit on the word clock instead of one bit later? If not, my post processing software could pick out the right bits and reassemble them if necessary.
If you were passing the stream through the Guzunty (which I thought you were), you would just have to cache 1 bit and emit it on the following clock cycle. That should not pose a resource problem, or do it in the driver software as you suggest.
This is only a matter of driver initialization. There has to be a application specific configuration driver anyway. Please add an issue at my github repo with the requirements (msb position, frame length, who generates the which clock.....) and I will add an appropriate driver soon.
@koalo: That would be this one? https://github.com/koalo/snd_pi_i2s_poor_dma
I'm curious to see what you've been doing. :-)
Oh I am sorry, it is this one: https://github.com/koalo/linux
Have you chosen your codec devices? I recall you were considering using WM8580As. A quick Google suggests that they aren't particularly obtainable. I tend to use Farnell for a lot of my parts and they have the NXP UDA1345TS which seems like it would do the job.
Do you still need a core or would you like me to take a look at it?
For a stereo codec, the CS4270 works quite nice.
Submitted issue for the driver to directly support the 1402G serial output format (almost I2S, but not quite).
From Florian:
I want to multiplex the I2S interface, but I don't know if your CPLD is large and fast enough (I have no experience with CPLDs, only with large FPGAs and they had much more capabilities than I ever used).
The basic idea is this: There is a master clock of about 12.288 MHz. There are two bitstreams clocked with 3.072 MHz. They have to be merged word-wise into a bitstream clocked with 6.144 MHz.