Open GoogleCodeExporter opened 9 years ago
Original comment by jan.trei...@gmail.com
on 8 May 2013 at 8:24
Intel's Performance Monitoring Unit Sharing Guide is attached.
http://software.intel.com/file/30388
Original comment by n...@verse.com
on 5 Nov 2013 at 2:08
Attachments:
Delayed to next release
Original comment by jan.trei...@gmail.com
on 22 Jan 2014 at 1:37
The paper is outdated. Further counters as Uncore (PCI based) and RAPL are not
addressed.
Therefore this issue is delayed.
Original comment by jan.trei...@gmail.com
on 8 May 2014 at 11:06
I really would like to see some method that checks whether the counters are
already in use - Intel PCM reports within its init phase if the counters are
not zeroed and ask to enforce a clearing.
But there is also a conflict with tools like PAPI that rely on the Linux kernel
perf_event interface: these tools do not set the MSRs directly and do not clean
up at the end. So monitoring a node as root using likwid (or Intel PCM) might
always fail if an application used the perf_event interface.
Original comment by bockelm...@org.dkrz.de
on 4 Aug 2014 at 9:09
The current trunk version checks the counter at the beginning. It skipps
counters where the control register is not empty. In general we wanted to avoid
additional register reads at the beginning as we have seen long access times
for the MSRs in particular situations. But these checks are needed so that we
can use common control files for e.g. SandyBridge and SandyBridge EP.
In the end, LIKWID zeros the control registers but leaves the counter registers
untouched.
Original comment by Thomas.R...@googlemail.com
on 28 Aug 2014 at 4:32
Original issue reported on code.google.com by
jan.trei...@gmail.com
on 3 Dec 2012 at 9:36