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HFF-Git / VCPU-32

This is a vintage design CPU with 32-bits. See the document in the VCPU-32-Documentation folder for a more detailed description.
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INstruction issues #13

Closed wesch closed 2 months ago

wesch commented 2 months ago

BV instruction

BV r, a( b ) BV a( b ) --> shouldn't it BV r,(b) ??

In general:

when regA and regB are used the mnemonic should always ...regA,regB

this affects CMR: currently CMR regR, regB, regA --> CMR regR, regA, regB DSR --> DSR<.A> regR, regB, regA, shamt --> DSR<.A> regR, regA, regB, shamt

HFF-Git commented 2 months ago

Sent from my iPadOn 15. Jun 2024, at 19:13, WolfgangE @.***> wrote: BV instruction BV r, a( b ) BV a( b ) --> shouldn't it BV r,(b) ??When R0 is specified as return link target, it would be convenient to omit it. Hence BV a(b).This will be quite often the case.In addition, we could also have a rule to omit “a” when it is the zero reg. Although possible, “b” should not be reg zero. In general: when regA and regB are used the mnemonic should always ...regA,regB this affects CMR: currently CMR regR, regB, regA --> CMR regR, regA, regBFor CMR certainly possible. DSR --> DSR<.A> regR, regB, regA, shamt --> DSR<.A> regR, regA, regB, shamtThe idea to reverse the order is that the 64-bit shift reg is built by regB:regA and not regA:regB. Wouldn’t it be more intuitive to specify the registers in the order as they are put into the shift register ?

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HFF-Git commented 2 months ago

Changed CMR instruction: oder of A and B in the assembly notation.

Changed the BV instruction: 99% of the use c cases are BV (b) to implement the return from a procedure. Although we could add register a, let's align the the instruction with the BR instruction. We only have register in "b". BR will shift "b" by 2 bits and branch IA relative, BV will use "b" as is segment base relative. Both instructions will place IA+4 in "r" as a return link option.

Fixed the document accordingly.

wesch commented 2 months ago

Instruction BV: what should be put in regR field when BV a( b )? Zero or it doesn't care

Sequence of regA and regB: makes sense for someone with deep understanding of the hardware :-) Ok. we keep it this way!

CMR: ok

HFF-Git commented 2 months ago

There are two formats:BV r, (b)BV (b)When r = 0, the second format looks nicer. But also BV r0, (b) is valid. Reg A field was dropped.DSR: the assembler can still put the two regs in the “right” order.DSR r, b, a The programmer sees the two refs in the intuitive order, the assembler puts them in b, an order.Sent from my iPadOn 16. Jun 2024, at 18:21, WolfgangE @.***> wrote: Instruction BV: what should be put in regR field when BV a( b )? Zero or it doesn't care Sequence of regA and regB: makes sense for someone with deep understanding of the hardware :-) Ok. we keep it this way! CMR: ok

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