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HFF-Git / VCPU-32

This is a vintage design CPU with 32-bits. See the document in the VCPU-32-Documentation folder for a more detailed description.
GNU General Public License v3.0
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Unclear description Operand Encoding #14

Open wesch opened 3 days ago

wesch commented 3 days ago

In section Operand Encoding for computational instructions

....... Operand mode 2 is the register indexed address mode, which will use a base register "b" and add an offset in "a" to it, forming the final byte address offset. The upper two bits select one of the segment registers SR4 .. SR7.

It is unlcear which two bits of what are used .

HFF-Git commented 3 days ago

“A” is added to “B” forms the byte address offset. The upper two bits of this offset select among the segment register SR4 to SR7. Zero maps to SR4, one to SR5 and so on.

HFF-Git commented 3 days ago

The same logic applies to mode 3. The upper two bits of the address formed by adding the offset encoded to”B” result in the final offset and the upper two bits select the segment register…