Closed wesch closed 5 months ago
Worked the examples, fixed the issues in the disassembler…
Viele Grüsse, Helmut
Am 26.03.2024 um 18:33 schrieb WolfgangE @.***>:
DD R7,R1(R5) (0x41c10015) Opmode 4 is correct 0x41c14015 Opmode 5 should give ADD.H --> instead ADD R7,R1(R5) 0x41c18015 Opmode 6 should give ADD.B --> instead ADD R7,R1(R5)
ADD R7,23(R8) (0x41c2002e) Opmode 8 is correct ADD R7,2071(S8, R1) (0x41c2102e) Opmode 8 seg = 1 ???
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SOLL: ADD R5,100(S2,R12) # Opmode 12 dis 0x414320C8 Ergebnis: ADD r5,4196(s2,r12) ????
Fixed. Accidentally encoded indexed as 14-bit field instead of 12-bit field.
Am 28.03.2024 um 11:02 schrieb WolfgangE @.***>:
SOLL: ADD R5,100(S2,R12) # Opmode 12 dis 0x414320C8 Ergebnis: ADD r5,4196(s2,r12) ????
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DD R7,R1(R5) (0x41c10015) Opmode 4 is correct 0x41c14015 Opmode 5 should give ADDH --> instead ADD R7,R1(R5) 0x41c18015 Opmode 6 should give ADDB --> instead ADD R7,R1(R5)
ADD R7,23(R8) (0x41c2002e) Opmode 8 is correct ADD R7,2071(S8, R1) (0x41c2102e) Opmode 8 seg = 1 ???
ADDH R7,23(R9) (0x41c2402e) Opmode 9 should be ADD R7,23(R9) (0x41c2402e)