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HFF-Git / VCPU-32

This is a vintage design CPU with 32-bits. See the document in the VCPU-32-Documentation folder for a more detailed description.
GNU General Public License v3.0
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Disassembler issues in 16-index regsiter branch #6

Closed wesch closed 5 months ago

wesch commented 5 months ago

soll ADD R15,2 dis 0x43C00004 ist ADD r15,0x2 please show in dec
soll ADD R15,R4 dis 0x43C20004 ist ADD r15,0,r4 error

all other modes are ok for ADD

Header of Simulator should show the version and branch

VCPU-32 Simulator, Version: B.00.02

HFF-Git commented 5 months ago

Zu 0: Done. It is now decimal.

Zu 1: This is a OpMode 1, SubOpMode 0 Instruction. To show that mode, I have added to the dissembler the „0,“ part to indicate that one of the parameter ( the A value ) is a zero value.

Am 29.03.2024 um 18:00 schrieb WolfgangE @.***>:

Mode Instruktion Instruction Result disassembler

0 ADD R15,2 dis 0x43C00004 ADD r15,0x2 please show in dec 1 1reg ADD R15,R4 dis 0x43C20004 ADD r15,0,r4 error

all other modes are ok for ADD

Header of Simulator should show the version and branch

VCPU-32 Simulator, Version: B.00.02

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