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HFF-Git / VCPU-32

This is a vintage design CPU with 32-bits. See the document in the VCPU-32-Documentation folder for a more detailed description.
GNU General Public License v3.0
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unclear operand encoding #9

Closed wesch closed 3 months ago

wesch commented 3 months ago

Decodoing ADD Instruction leads to dis 0x41C84064 -->ADDB r7, (s0,r4) (0x41c84064) dis 0x41C94064 -->ADDH r7, (s2,r4) (0x41c94064) -- Why S2? only change was from byte to halfword dis 0x41CA4064 -->ADD r7, (s0,r4) (0x41ca4064) dis 0x41CB4064-->ADDdw r7, (s2,r4) (0x41cb4064) --> ok not implemented yet but again s2

HFF-Git commented 3 months ago

Hallo Wolfgang,

Ich habe es korrigiert. Wir reden hier von Mode 2, also Register Indexed.

VCPU-32 Simulator, Version: B.00.05 Git Branch: Main Branch (0) ->dis 0x41C84064 ADDB r7, r6(r4) (0x41c84064) (1) ->dis 0x41C94064 ADDH r7, r6(r4) (0x41c94064) (2) ->dis 0x41CA4064 ADD r7, r6(r4) (0x41ca4064) (3) ->dis 0x41CB4064 ADDdw r7, r6(r4) (0x41cb4064) (4) ->

Viele Grüsse, Helmut

Am 03.06.2024 um 17:03 schrieb WolfgangE @.***>:

Decodoing ADD Instruction leads to dis 0x41C84064 -->ADDB r7, (s0,r4) (0x41c84064) dis 0x41C94064 -->ADDH r7, (s2,r4) (0x41c94064) -- Why S2? only change was from byte to halfword dis 0x41CA4064 -->ADD r7, (s0,r4) (0x41ca4064) dis 0x41CB4064-->ADDdw r7, (s2,r4) (0x41cb4064) --> ok not implemented yet but again s2

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HFF-Git commented 3 months ago

Corrected.