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HKUSTGZ-MICS-LYU / FlattenRTL

This is a python repo for flattening Verilog
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Support parse the verilog with define #4

Closed hanm2019 closed 1 month ago

hanm2019 commented 1 month ago

Hello,

I am using this tool to process Verilog files, and I wanted to ask if it supports Verilog files that contain macro definitions (\'define, `ifdef, `ifndef`, etc.). If not, are there any plans to implement support for macro processing in future releases?

Additionally, if macro support is not natively available, could you provide any suggestions or workarounds to preprocess these macros before passing the Verilog files to this tool?

Thank you for your help!

Jzjerry commented 1 month ago

Hi,

Currently, we don't handle macros in our tools, but you can use iverilog -E to preprocess them.