AttributeError: 'List_of_variable_port_identifiersContext' object has no attribute 'range_'

[hanm2019]

I meet an Error when I try to flatten these code:

gcd.v:

module gcd (
    input wire clk,
    input wire rst,
    input wire start,
    input wire [31:0] a,
    input wire [31:0] b,
    output reg done,
    output reg [31:0] result
);

    reg [31:0] x, y;
    reg [1:0] state;

    localparam IDLE = 2'b00;
    localparam CALC = 2'b01;
    localparam DONE = 2'b10;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            state <= IDLE;
            done <= 0;
            result <= 0;
            x <= 0;
            y <= 0;
        end else begin
            case (state)
                IDLE: begin
                    if (start) begin
                        x <= a;
                        y <= b;
                        state <= CALC;
                    end
                end

                CALC: begin
                    if (y == 0) begin
                        result <= x;
                        done <= 1;
                        state <= DONE;
                    end else begin
                        if (x > y) begin
                            x <= x - y;
                        end else begin
                            y <= y - x;
                        end
                    end
                end

                DONE: begin
                    if (!start) begin
                        done <= 0;
                        state <= IDLE;
                    end
                end

            endcase
        end
    end
endmodule

gcd_top.v:

module gcd_remu (
    input wire clk,    
    input wire rst,   

    input wire start_dut,    
    input wire [31:0] a_dut,   
    input wire [31:0] b_dut, 
    output wire done_dut,
    output wire [31:0] result_dut,

    input wire start_other, 
    input wire [31:0] a_other, 
    input wire [31:0] b_other, 
    output wire done_other, 
    output wire [31:0] result_other
);

    gcd dut (
        .clk(clk),
        .rst(rst),
        .start(start_dut),
        .a(a_dut),
        .b(b_dut),
        .done(done_dut),
        .result(result_dut)
    );

    gcd remu (
        .clk(clk),
        .rst(rst),
        .start(start_other),
        .a(a_other),
        .b(b_other),
        .done(done_other),
        .result(result_other)
    );

endmodule

Error:

INFO] Formatting the module gcd
Traceback (most recent call last):
  File "main.py", line 83, in <module>
    main()
  File "main.py", line 39, in main
    formatted_design = preprocess.format_file(design)
  File "preprocess.py", line 613, in format_file
    visitor.visit(design)
  File ".local/lib/python3.8/site-packages/antlr4/tree/Tree.py", line 34, in visit
    return tree.accept(self)
  File "antlr4_verilog/verilog/VerilogParser.py", line 3925, in accept
    return visitor.visitSource_text(self)
  File "antlr4_verilog/verilog/VerilogParserVisitor.py", line 44, in visitSource_text
    return self.visitChildren(ctx)
  File ".local/lib/python3.8/site-packages/antlr4/tree/Tree.py", line 44, in visitChildren
    childResult = c.accept(self)
  File "antlr4_verilog/verilog/VerilogParser.py", line 3990, in accept
    return visitor.visitDescription(self)
  File "antlr4_verilog/verilog/VerilogParserVisitor.py", line 49, in visitDescription
    return self.visitChildren(ctx)
  File ".local/lib/python3.8/site-packages/antlr4/tree/Tree.py", line 44, in visitChildren
    childResult = c.accept(self)
  File "antlr4_verilog/verilog/VerilogParser.py", line 4087, in accept
    return visitor.visitModule_declaration(self)
  File "preprocess.py", line 608, in visitModule_declaration
    self.__format_design(self.module)
  File "preprocess.py", line 583, in __format_design
    visitor.visitModule_declaration(tree)
  File "preprocess.py", line 45, in visitModule_declaration
    self.__visit_module_declaration(ctx)
  File "preprocess.py", line 53, in __visit_module_declaration
    self.__visit_port_list(child)
  File "preprocess.py", line 182, in __visit_port_list
    self.__visit_port_list(child)
  File "preprocess.py", line 182, in __visit_port_list
    self.__visit_port_list(child)
  File "preprocess.py", line 182, in __visit_port_list
    self.__visit_port_list(child)
  [Previous line repeated 1 more time]
  File "preprocess.py", line 177, in __visit_port_list
    if child.parentCtx.parentCtx.range_() !=None:
AttributeError: 'List_of_variable_port_identifiersContext' object has no attribute 'range_'

[MrWater98]

Thank you for bringing this issue to our attention. We have recently shifted our focus towards maintaining the 'sv' branch, which addresses many bugs present in the earlier versions. However, please note that it is crucial to install a higher version of antlr to ensure compatibility with these fixes.

We have noticed that our support for localparam is not optimal at the moment. To assist you further, we have slightly modified your Verilog code. You should be able to use the modified code provided below. Additionally, to facilitate running the code, we recommend adding a filelist.f.

module gcd (
    input clk,
    input rst,
    input start,
    input [31:0] a,
    input [31:0] b,
    output reg done,
    output reg [31:0] result
);

    reg [31:0] x, y;
    reg [1:0] state;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            state <= 2'b10;
            done <= 0;
            result <= 0;
            x <= 0;
            y <= 0;
        end else begin
            case (state)
                2'b10: begin
                    if (start) begin
                        x <= a;
                        y <= b;
                        state <= 2'b10;
                    end
                end

                2'b10: begin
                    if (y == 0) begin
                        result <= x;
                        done <= 1;
                        state <= 2'b10;
                    end else begin
                        if (x > y) begin
                            x <= x - y;
                        end else begin
                            y <= y - x;
                        end
                    end
                end

                2'b10: begin
                    if (!start) begin
                        done <= 0;
                        state <= 2'b10;
                    end
                end

            endcase
        end
    end
endmodule

module gcd_remu (
    input clk,    
    input rst,   

    input start_dut,    
    input [31:0] a_dut,   
    input [31:0] b_dut, 
    output done_dut,
    output [31:0] result_dut,

    input start_other, 
    input [31:0] a_other, 
    input [31:0] b_other, 
    output done_other, 
    output [31:0] result_other
);

    gcd dut (
        .clk(clk),
        .rst(rst),
        .start(start_dut),
        .a(a_dut),
        .b(b_dut),
        .done(done_dut),
        .result(result_dut)
    );

    gcd remu (
        .clk(clk),
        .rst(rst),
        .start(start_other),
        .a(a_other),
        .b(b_other),
        .done(done_other),
        .result(result_other)
    );

endmodule

Please try the provided code and let us know if you encounter any further issues.