HSD-ESD / VHDL-by-HGB

VHDL-by-HGB is a VS-Code extension for VHDL.
https://hsd-esd.github.io/VHDL-by-HGB/
GNU General Public License v3.0
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Design Hierarchy View #14

Open std-rubic opened 6 months ago

std-rubic commented 6 months ago

A view to navigate through the design (hierarchy <-> Source files) would be a very helpful feature of this extension. something like the (a bit imprecise) vhdl-hierarchy extension... https://marketplace.visualstudio.com/items?itemName=JesperRaemaekers.vhdl-hierarchy

jakobjung10 commented 3 months ago

Hi @std-rubic,

there is an outline view showing the hierarchy of a single file (with the information from the Language Server). outline-view

However, i think you are talking about the hierarchy of the whole project. In this case, a custom view must be implemented. It would be optimal to use a specific LSP-request to get the hierarchy information from the Language Server.

Currently, there is no such LSP-request implemented in VHDL_LS. However, if you take a look at the LSP-specification there is no LSP-request covering that specific scenario for the design-hierarchy.

I think the closest request are:

Therefore, an issue must be created at VHDL_LS, but i am not sure if this method is optimal...

Another approach would be that the user specificies the top-level entity. From there, you could send a document-symbol-request to the Language Server (which is implemented in VHDL_LS). I think, from the returned information the children of the top-level-entity can be shown and on the client-side you could query the children of the whole project recursively. However, querying from the client-side is slower, an indirect route and possibly not that optimal, too...

Maybe, the already existing outline-view in the client can be made recursive from the server-side (not sure).

For me, the VHDL hierarchy-extension did not work btw.

std-rubic commented 2 months ago

Hi Jacobjung10, thanks for sharing the ideas. When i unterstand the vhdl-ls issue 219 right there ist Work in Progress for a bigger API concept, which could enable helpful functionality for this topic.

https://github.com/VHDL-LS/rust_hdl/issues/219