search

Hagiwara-shc / j202_soc

Apache License 2.0
4 stars 0 forks source link

Document SystemVerilog to Verilog process #1

Open xobs opened 1 year ago

xobs commented 1 year ago

Hi! Congratulations on the tapeout.

In looking through your build system, it seems like you have checked in a synthesized netlist version of the core:

https://github.com/Hagiwara-shc/j202_soc/blob/11c2b4f674091386fda6144f4a8196e83cf050f9/openlane/j202_soc/config.tcl#L92-L94

Would it be possible to document how you generated this netlist, and how we can reproduce your results?

xobs commented 1 year ago

cc @proppy