The Verilog code generator in netlistDB was build mainly for testing purposes. Currently I am finishing the hdlConvertor library which will be used to load and dump designs from/to Vhdl/Verilog.
The hdlConvertor uses abstract AST, this AST can be easily converted to netlistDB format. The opposite direction would require translation of unsupported code constructs and types.
The Verilog code generator in netlistDB was build mainly for testing purposes. Currently I am finishing the hdlConvertor library which will be used to load and dump designs from/to Vhdl/Verilog.
The hdlConvertor uses abstract AST, this AST can be easily converted to netlistDB format. The opposite direction would require translation of unsupported code constructs and types.