Open lukaswagner opened 5 years ago
tl;dr: this issue leads to a half year fulltime job (for someone with low-level c++/gcc knowledge)
currently, the firmware's performance is limited by both cores accessing the same blocks of RAM sometimes, which results in slowdowns as one core has to wait. the best solution would be to write a custom memory management, as well as customize the way the binary and static data is placed into RAM (see gcc linker map files). the first step for this would be to create a map of the available RAM addresses, both by using the hardware reference manual and writing a test application which tries to allocate different areas of memory. this first step shouldn't take too long, but the actual optimization would be a master thesis worth of work.
thanks!
@lukaswagner could you provide a description ? thanks !