HelTecAutomation / CubeCell-Arduino

Heltec CubeCell Series (based on ASR6501, ASR6502 chip) Arduino support.
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How to read the internal temperature? #238

Open tkrahn opened 2 years ago

tkrahn commented 2 years ago

According to the PSoC 4100 family datasheet the micro controller has an internal temperature sensor.

Page 7: Temperature Sensor PSoC 4100 has one on-chip temperature sensor This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using Cypress supplied software that includes calibration and linearization.

Is it in any way possible to read it out through the ADC? If so, is there some sample code how to do this?

The reason why I need this is for an extremely light GPS tracker for a small unmanned balloon. We try to save every micro-gram of weight, but temperature would be an important telemetry reading. Therefore external sensors are not an option.

Mr-HaleYa commented 2 years ago

They need to add the DieTemp.c and DieTemp.h files into the cores/asr650x/projects/PSoC4/ folder

/*******************************************************************************
* File Name: DieTemp.c
* Version 1.0
*
* Description:
*  This file provides the source code of APIs for the DieTemp_P4 component.
*
*******************************************************************************
* Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#include "DieTemp.h"

/*******************************************************************************
* Function Name: DieTemp_CountsTo_Celsius
********************************************************************************
*
* Summary:
*  Converts the ADC output to degrees Celsius.
*
* Parameters:
*  int32 adcCounts:
*   Result from the ADC Conversion
*
* Return:
*  Temperature in degrees Celsius
*
* Global variables:
*  None
*
*******************************************************************************/
int32 DieTemp_CountsTo_Celsius(int32 adcCounts)
{
    int32 tempCelsius;
    int32 tInitial;
    int32 tAdjust;
    int32 offsetReg;
    int32 multReg;

    offsetReg = (int16)DieTemp_SAR_TEMP_OFFSET_REG;
    multReg   = (int16)DieTemp_SAR_TEMP_MULTIPLIER_REG;
    /* Calculate tInitial in Q16.16 */
    tInitial = (adcCounts * multReg) + (offsetReg * DieTemp_SAR_TEMP_OFFSET_MULT);

    if(tInitial >= DieTemp_DUAL_SLOPE_CORRECTION)
    {
        /* Shift (100 - tInitial) by 4 bits to prevent scale-adjustment from overflowing. */
        /* Then divide by the integer bits of (100 - cutoff) to end up with a Q16.16 tAdjust */
        tAdjust = (DieTemp_SCALE_ADJUSTMENT * (((int32)DieTemp_HIGH_TEMPERATURE - tInitial)
            / (int32)DieTemp_SCALE_ADJUSTMENT_DIVIDER)) /
            (((int32)DieTemp_HIGH_TEMPERATURE - (int32)DieTemp_DUAL_SLOPE_CORRECTION) /
            DieTemp_SAR_TEMP_DIVIDER);
    }
    else
    {
        /* Shift (40 + tInitial) by 4 bits to prevent scale-adjustment from overflowing. */
        /* Then divide by the integer bits of (40 + cutoff) to end up with a Q16.16 tAdjust */
        tAdjust = ((int32)DieTemp_SCALE_ADJUSTMENT * (((int32)DieTemp_LOW_TEMPERATURE + tInitial)
           / (int32)DieTemp_SCALE_ADJUSTMENT_DIVIDER)) /
            (((int32)DieTemp_LOW_TEMPERATURE + (int32)DieTemp_DUAL_SLOPE_CORRECTION) /
            (int32)DieTemp_SAR_TEMP_DIVIDER);
    }

    /* Add tInitial + tAdjust + 0.5 to round to nearest int. Shift off frac bits, and return. */
    tempCelsius = tInitial + tAdjust + DieTemp_HALF_OF_ONE;

    return (tempCelsius / DieTemp_SAR_TEMP_OFFSET_DIVIDER);
}

/* [] END OF FILE */
/*******************************************************************************
* File Name: DieTemp.h
* Version 1.0
*
* Description:
*  This file provides constants and parameter values for the DieTemp_P4
*  component.
*
********************************************************************************
* Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#if !defined(CY_DIE_TEMP_DieTemp_H)
#define CY_DIE_TEMP_DieTemp_H

#include "cytypes.h"
#include "cyfitter.h"
#include "CyLib.h"
#include "cydevice_trm.h"

/***************************************
*        API constants
***************************************/

#define DieTemp_SAR_TEMP_MULTIPLIER_REG    (*(reg16 *) CYREG_SFLASH_SAR_TEMP_MULTIPLIER)
#define DieTemp_SAR_TEMP_MULTIPLIER_PTR    ( (reg16 *) CYREG_SFLASH_SAR_TEMP_MULTIPLIER)
#define DieTemp_SAR_TEMP_OFFSET_REG        (*(reg16 *) CYREG_SFLASH_SAR_TEMP_OFFSET)
#define DieTemp_SAR_TEMP_OFFSET_PTR        ( (reg16 *) CYREG_SFLASH_SAR_TEMP_OFFSET)

#define DieTemp_SAR_TEMP_OFFSET_SHIFT      (10u)
#define DieTemp_SAR_TEMP_OFFSET_MULT       (0x400)
#define DieTemp_SAR_TEMP_OFFSET_DIVIDER    (0x10000)
#define DieTemp_SAR_TEMP_SHIFT             (16u)
#define DieTemp_SAR_TEMP_DIVIDER           (0x10000)
#define DieTemp_SCALE_ADJUSTMENT_DIVIDER   (16u)
#define DieTemp_HALF_OF_ONE                ((int32)1u << (DieTemp_SAR_TEMP_SHIFT - 1u))

/* (effectively 0.5 << 4u) 0.5 in Q28.4 format */
#define DieTemp_SCALE_ADJUSTMENT           (8)
/* 15 in Q16.16 format */
#define DieTemp_DUAL_SLOPE_CORRECTION      (0xF0000)
/* 100 in Q16.16 format */
#define DieTemp_HIGH_TEMPERATURE           (0x640000)
/* 40 in Q16.16 format */
#define DieTemp_LOW_TEMPERATURE            (0x280000)

/***************************************
*        Function Prototypes
***************************************/

int32 DieTemp_CountsTo_Celsius(int32 adcCounts);

#endif /* CY_DIE_TEMP_DieTemp_H */

/* [] END OF FILE */

then since its using the ASR probably some code in cores/asr650x/cores/ASR_Arduino.h and a corresponding .c file not sure what else they would need to do but it Can be added since like you said the SOC supports it I would personally love to see it since I wouldn't mind an onboard temp sensor even if its technically a die sensor

you could even try doing it yourself with that code and some documentation reading 🤷‍♂️ 🙃

tkrahn commented 2 years ago

Thanks Mr-HaleYa, Your code nicely shows how to calculate the temperature. This is very useful, once you have the adcCounts. However what I'm trying to figure out is how to get the adcCounts for the Die Temperature Sensor in the first place.

I've found from https://community.infineon.com/t5/Knowledge-Base-Articles/Calculate-Die-Temperature-with-DieTemp-Component-in-PSoC-4-KBA229527/ta-p/260201 the following code:

int32 u32 DieTempGet(void) {
    int16 adc_count;
    uint32 u32_regTemp;
    int32 Celsius;
    u32_regTemp = CY_GET_REG32(0x403A0000u);

    CY_SET_REG32(0x403A0000u, ((u32_regTemp & 0xFFFFFF00u) | 0x00000040u)); // Before DieTemp measurement, change ADC Vref connection to internal Vref(1.2-V)
    ADC_EnableInjection(); // INJ Channel Enable
    ADC_StartConvert();    // ADC Convert start
    while(0u == ADC_IsEndConversion(ADC_RETURN_STATUS_INJ)){}
    adc_count = ADC_GetResult16((uint32)INJ_CHN);

    // DO NOT need adc count adjusted/calibrated, because Vref has been changed to internal vref (1.2-V)
    Celsius = DieTemp_CountsTo_Celsius(adc_count); // get temp celsius Degree
    CY_SET_REG32(0x403A0000u, u32_regTemp); // after measurement, restore original ADC vref connection register

    return Celsius;
 }

doesn't compile because ADC_EnableInjection() and ADC_StartConvert() are not declared.

I was trying the following:

/*  Trying to get the ADC value of  internal temperature sensor of PSoC 4100 */
uint16_t getOnChipTempAdc(void)
{
    float temp = 0;
    uint16_t volt;
    uint8_t pin = ADC2; // internal temperature sensor of PSoC 4100 ????

    pinMode(VBAT_ADC_CTL,OUTPUT);
    digitalWrite(VBAT_ADC_CTL,LOW);

    for(int i=0;i<50;i++) //read 50 times and get average
        temp+=analogReadmV(pin);
    volt = 2 * temp / 50;

    pinMode(VBAT_ADC_CTL, INPUT);

    // volt = volt*2;
    return volt;
}

/*  Get the ADC value in mV of different ADC Pins (ADC2, ADC3) */
uint16_t getAdcMilliVolt(uint16_t pin)
{
    float temp = 0;
    uint16_t volt;

    pinMode(VBAT_ADC_CTL,OUTPUT);
    digitalWrite(VBAT_ADC_CTL,LOW);

    for(int i=0;i<50;i++) //read 50 times and get average
        temp+=analogReadmV(pin);
    volt = 2 * temp / 50;

    pinMode(VBAT_ADC_CTL, INPUT);

    // volt = volt*2;
    return volt;
}

but I'm not sure if I'm reading the correct ADC "pin" and if the power on the internal diode is enabled correctly. The adc count doesn't seem to reflect anything related to a temperature.

Mr-HaleYa commented 2 years ago

but I'm not sure if I'm reading the correct ADC "pin" and if the power on the internal diode is enabled correctly. The adc count doesn't seem to reflect anything related to a temperature.

ya, your code is not accessing the internal ADC but instead is testing the external ADC pin(s).


oh, I see. looking at this repos code it doesn't look like they use the internal ADC at all... so you would need the files to enable and control it Those functions you listed need 2 files in cores/asr650x/projects/PSoC4/

/*******************************************************************************
* File Name: ADC.h
* Version 2.50
*
* Description:
*  This file contains the function prototypes and constants used in
*  the Sequencing Successive Approximation ADC Component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#if !defined(CY_ADC_SAR_SEQ_ADC_H)
#define CY_ADC_SAR_SEQ_ADC_H

#include "cytypes.h"
#include "CyLib.h"

/***************************************
*      Data Struct Definition
***************************************/

/* Sleep Mode API Support */
typedef struct
{
    uint8 enableState;
    uint32 dftRegVal;
} ADC_BACKUP_STRUCT;

/**************************************
*    Enumerated Types and Parameters
**************************************/

/*  Clock Source setting constants */
#define ADC__EXTERNAL 0
#define ADC__INTERNAL 1

/*  Sample Mode setting constants */
#define ADC__FREERUNNING 0
#define ADC__HARDWARESOC 1

/*  Reference type setting constants */
#define ADC__VDDA_2 0
#define ADC__VDDA 1
#define ADC__INTERNAL1024 2
#define ADC__INTERNAL1024BYPASSED 3
#define ADC__INTERNALVREF 4
#define ADC__INTERNALVREFBYPASSED 5
#define ADC__VDDA_2BYPASSED 6
#define ADC__EXTERNALVREF 7

/* Input buffer gain setting constants */
#define ADC__DISABLED 0
#define ADC__ONE 1
#define ADC__TWO 2
#define ADC__FOUR 3
#define ADC__EIGHT 4
#define ADC__SIXTEEN 5

/* Negative input setting sonstants in single ended mode */
#define ADC__VSS 0
#define ADC__VREF 1
#define ADC__OTHER 2

/* Compare mode setting constants:
*    Mode0 - Disable
*    Mode1 - Result < Low_Limit
*    Mode2 - Low_Limit <= Result < High_Limit
*    Mode3 - High_Limit <= Result
*    Mode4 - (Result < Low_Limit) or (High_Limit <= Result)
*/
#define ADC__MODE0 0
#define ADC__MODE1 1
#define ADC__MODE2 2
#define ADC__MODE3 3

#define ADC__RES8 0
#define ADC__RES10 1

#define ADC__RIGHT 0
#define ADC__LEFT 1

#define ADC__FSIGNED 1
#define ADC__FUNSIGNED 0

#define ADC__ACCUMULATE 0
#define ADC__FIXEDRESOLUTION 1

/***************************************
*   Conditional Compilation Parameters
****************************************/ 

#define ADC_CY_SAR_IP_VER0                  (0u)
#define ADC_CY_SAR_IP_VER1                  (1u)

#if (CY_PSOC4_4100 || CY_PSOC4_4200)
    #define ADC_CY_SAR_IP_VER              (ADC_CY_SAR_IP_VER0)
#else /* Other devices */
    #define ADC_CY_SAR_IP_VER              (ADC_CY_SAR_IP_VER1)
#endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */

/***************************************
*    Initial Parameter Constants
***************************************/
#define ADC_DEFAULT_SAMPLE_MODE_SEL        (0u)
#define ADC_DEFAULT_VREF_SEL               (2u)
#define ADC_DEFAULT_NEG_INPUT_SEL          (1u)
#define ADC_DEFAULT_ALT_RESOLUTION_SEL     (0u)
#define ADC_DEFAULT_JUSTIFICATION_SEL      (0u)
#define ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL (1u)
#define ADC_DEFAULT_SE_RESULT_FORMAT_SEL   (0u)
#define ADC_DEFAULT_CLOCK_SOURCE           (1u)
#define ADC_DEFAULT_VREF_MV_VALUE          (1024)
#define ADC_DEFAULT_BUFFER_GAIN            (0u)
#define ADC_DEFAULT_AVG_SAMPLES_NUM        (2u)
#define ADC_DEFAULT_AVG_SAMPLES_DIV        (2u < 4u) ? (int16)(0x100u >> (7u - 2u)) : (int16)(0x100u >> 4u)
#define ADC_DEFAULT_AVG_MODE               (1u)
#define ADC_MAX_RESOLUTION                 (12u)
#define ADC_DEFAULT_LOW_LIMIT              (0u)
#define ADC_DEFAULT_HIGH_LIMIT             (2047u)
#define ADC_DEFAULT_COMPARE_MODE           (0u)
#define ADC_DEFAULT_ACLKS_NUM              (1001u)
#define ADC_DEFAULT_BCLKS_NUM              (4u)
#define ADC_DEFAULT_CCLKS_NUM              (4u)
#define ADC_DEFAULT_DCLKS_NUM              (4u)
#define ADC_TOTAL_CHANNELS_NUM             (5u)
#define ADC_SEQUENCED_CHANNELS_NUM         (4u)
#define ADC_DEFAULT_EN_CHANNELS            (15u)
#define ADC_NOMINAL_CLOCK_FREQ             (1000000)
#define ADC_INJ_CHANNEL_ENABLED            (1u)
#define ADC_IRQ_REMOVE                     (0u)

/* Determines whether the configuration contains external negative input. */
#define ADC_SINGLE_PRESENT                 (0u)
#define ADC_CHANNELS_MODE                  (4u)
#define ADC_MAX_CHANNELS_EN_MASK           (0xffffu >> (16u - ADC_SEQUENCED_CHANNELS_NUM))

/***************************************
*        Function Prototypes
***************************************/

void ADC_Start(void);
void ADC_Stop(void);
void ADC_Init(void);
void ADC_Enable(void);
void ADC_StartConvert(void);
void ADC_StopConvert(void);
uint32 ADC_IsEndConversion(uint32 retMode);
int16 ADC_GetResult16(uint32 chan);
void ADC_SetChanMask(uint32 mask);
void ADC_SetLowLimit(uint32 lowLimit);
void ADC_SetHighLimit(uint32 highLimit);
void ADC_SetLimitMask(uint32 mask);
void ADC_SetSatMask(uint32 mask);
void ADC_SetOffset(uint32 chan, int16 offset);
void ADC_SetGain(uint32 chan, int32 adcGain);
#if(ADC_INJ_CHANNEL_ENABLED)
    void ADC_EnableInjection(void);
#endif /* ADC_INJ_CHANNEL_ENABLED */
#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT)
    int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts);
    int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts);
    float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts);
#endif /* End ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */
void ADC_Sleep(void);
void ADC_Wakeup(void);
void ADC_SaveConfig(void);
void ADC_RestoreConfig(void);

CY_ISR_PROTO( ADC_ISR );

/**************************************
*           API Constants
**************************************/
/* Constants for Sleep mode states */
#define ADC_DISABLED                   (0x00u)
#define ADC_ENABLED                    (0x01u)
#define ADC_STARTED                    (0x02u)
#define ADC_BOOSTPUMP_ENABLED          (0x04u)

/*   Constants for IsEndConversion() "retMode" parameter  */
#define ADC_RETURN_STATUS              (0x01u)
#define ADC_WAIT_FOR_RESULT            (0x02u)
#define ADC_RETURN_STATUS_INJ          (0x04u)
#define ADC_WAIT_FOR_RESULT_INJ        (0x08u)

#define ADC_MAX_FREQUENCY              (18000000)       /*18Mhz*/

#define ADC_RESOLUTION_12              (12u)
#define ADC_RESOLUTION_10              (10u)
#define ADC_RESOLUTION_8               (8u)

#define ADC_10US_DELAY                 (10u)

#define ADC_10V_COUNTS                 (10.0F)
#define ADC_10MV_COUNTS                (10000)
#define ADC_10UV_COUNTS                (10000000L)

/***************************************
* Global variables external identifier
***************************************/

extern uint8 ADC_initVar;
extern volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM];
extern volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM];

/***************************************
*              Registers
***************************************/

#define ADC_SAR_CTRL_REG                (*(reg32 *) ADC_cy_psoc4_sar__SAR_CTRL )
#define ADC_SAR_CTRL_PTR                ( (reg32 *) ADC_cy_psoc4_sar__SAR_CTRL )

#define ADC_SAR_SAMPLE_CTRL_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL )
#define ADC_SAR_SAMPLE_CTRL_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL )

#define ADC_SAR_SAMPLE_TIME01_REG       (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 )
#define ADC_SAR_SAMPLE_TIME01_PTR       ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 )

#define ADC_SAR_SAMPLE_TIME23_REG       (*(reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 )
#define ADC_SAR_SAMPLE_TIME23_PTR       ( (reg32 *) ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 )

#define ADC_SAR_RANGE_THRES_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_THRES )
#define ADC_SAR_RANGE_THRES_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_THRES )

#define ADC_SAR_RANGE_COND_REG          (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_COND )
#define ADC_SAR_RANGE_COND_PTR          ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_COND )

#define ADC_SAR_CHAN_EN_REG             (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_EN )
#define ADC_SAR_CHAN_EN_PTR             ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_EN )

#define ADC_SAR_START_CTRL_REG          (*(reg32 *) ADC_cy_psoc4_sar__SAR_START_CTRL )
#define ADC_SAR_START_CTRL_PTR          ( (reg32 *) ADC_cy_psoc4_sar__SAR_START_CTRL )

#define ADC_SAR_DFT_CTRL_REG            (*(reg32 *) ADC_cy_psoc4_sar__SAR_DFT_CTRL )
#define ADC_SAR_DFT_CTRL_PTR            ( (reg32 *) ADC_cy_psoc4_sar__SAR_DFT_CTRL )

#define ADC_SAR_CHAN_CONFIG_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 )
#define ADC_SAR_CHAN_CONFIG_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 )
#define ADC_SAR_CHAN_CONFIG_IND         ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00

#define ADC_SAR_CHAN_WORK_REG           (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK00 )
#define ADC_SAR_CHAN_WORK_PTR           ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK00 )

#define ADC_SAR_CHAN_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 )
#define ADC_SAR_CHAN_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 )
#define ADC_SAR_CHAN_RESULT_IND         ADC_cy_psoc4_sar__SAR_CHAN_RESULT00

#define ADC_SAR_CHAN0_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 )
#define ADC_SAR_CHAN0_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 )

#define ADC_SAR_CHAN1_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 )
#define ADC_SAR_CHAN1_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 )

#define ADC_SAR_CHAN2_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 )
#define ADC_SAR_CHAN2_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 )

#define ADC_SAR_CHAN3_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 )
#define ADC_SAR_CHAN3_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 )

#define ADC_SAR_CHAN4_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 )
#define ADC_SAR_CHAN4_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 )

#define ADC_SAR_CHAN5_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 )
#define ADC_SAR_CHAN5_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 )

#define ADC_SAR_CHAN6_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 )
#define ADC_SAR_CHAN6_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 )

#define ADC_SAR_CHAN7_RESULT_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 )
#define ADC_SAR_CHAN7_RESULT_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 )

#if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0)
    #define ADC_SAR_CHAN8_RESULT_REG     (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 )
    #define ADC_SAR_CHAN8_RESULT_PTR     ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 )

    #define ADC_SAR_CHAN9_RESULT_REG     (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 )
    #define ADC_SAR_CHAN9_RESULT_PTR     ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 )

    #define ADC_SAR_CHAN10_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 )
    #define ADC_SAR_CHAN10_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 )

    #define ADC_SAR_CHAN11_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 )
    #define ADC_SAR_CHAN11_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 )

    #define ADC_SAR_CHAN12_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 )
    #define ADC_SAR_CHAN12_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 )

    #define ADC_SAR_CHAN13_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 )
    #define ADC_SAR_CHAN13_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 )

    #define ADC_SAR_CHAN14_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 )
    #define ADC_SAR_CHAN14_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 )

    #define ADC_SAR_CHAN15_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 )
    #define ADC_SAR_CHAN15_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 )
#endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */

#define ADC_SAR_CHAN_WORK_VALID_REG     (*(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID)
#define ADC_SAR_CHAN_WORK_VALID_PTR     ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID)

#define ADC_SAR_CHAN_RESULT_VALID_REG  ( *(reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID )
#define ADC_SAR_CHAN_RESULT_VALID_PTR  ( (reg32 *) ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID )

#define ADC_SAR_STATUS_REG              (*(reg32 *) ADC_cy_psoc4_sar__SAR_STATUS )
#define ADC_SAR_STATUS_PTR              ( (reg32 *) ADC_cy_psoc4_sar__SAR_STATUS )

#define ADC_SAR_AVG_START_REG           (*(reg32 *) ADC_cy_psoc4_sar__SAR_AVG_STAT )
#define ADC_SAR_AVG_START_PTR           ( (reg32 *) ADC_cy_psoc4_sar__SAR_AVG_STAT )

#define ADC_SAR_INTR_REG                (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR )
#define ADC_SAR_INTR_PTR                ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR )

#define ADC_SAR_INTR_SET_REG            (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_SET )
#define ADC_SAR_INTR_SET_PTR            ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_SET )

#define ADC_SAR_INTR_MASK_REG           (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASK )
#define ADC_SAR_INTR_MASK_PTR           ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASK )

#define ADC_SAR_INTR_MASKED_REG         (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASKED )
#define ADC_SAR_INTR_MASKED_PTR         ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_MASKED )

#define ADC_SAR_SATURATE_INTR_REG       (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR )
#define ADC_SAR_SATURATE_INTR_PTR       ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR )

#define ADC_SAR_SATURATE_INTR_SET_REG   (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET )
#define ADC_SAR_SATURATE_INTR_SET_PTR   ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET )

#define ADC_SAR_SATURATE_INTR_MASK_REG (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK )
#define ADC_SAR_SATURATE_INTR_MASK_PTR ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK )

#define ADC_SAR_SATURATE_INTR_MASKED_REG \
                                                 (*(reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED )
#define ADC_SAR_SATURATE_INTR_MASKED_PTR \
                                                 ( (reg32 *) ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED )

#define ADC_SAR_RANGE_INTR_REG          (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR )
#define ADC_SAR_RANGE_INTR_PTR          ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR )

#define ADC_SAR_RANGE_INTR_SET_REG      (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET )
#define ADC_SAR_RANGE_INTR_SET_PTR      ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET )

#define ADC_SAR_RANGE_INTR_MASK_REG     (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK )
#define ADC_SAR_RANGE_INTR_MASK_PTR     ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK )

#define ADC_SAR_RANGE_INTR_MASKED_REG   (*(reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED )
#define ADC_SAR_RANGE_INTR_MASKED_PTR   ( (reg32 *) ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED )

#define ADC_SAR_INTR_CAUSE_REG          (*(reg32 *) ADC_cy_psoc4_sar__SAR_INTR_CAUSE )
#define ADC_SAR_INTR_CAUSE_PTR          ( (reg32 *) ADC_cy_psoc4_sar__SAR_INTR_CAUSE )

#if(ADC_INJ_CHANNEL_ENABLED)
    #define ADC_SAR_INJ_CHAN_CONFIG_REG \
                                                 (*(reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG )
    #define ADC_SAR_INJ_CHAN_CONFIG_PTR    \
                                                 ( (reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_CHAN_CONFIG )

    #define ADC_SAR_INJ_RESULT_REG    (*(reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_RESULT )
    #define ADC_SAR_INJ_RESULT_PTR    ( (reg32 *) ADC_cy_psoc4_sarmux_8__SAR_INJ_RESULT )
#endif /* ADC_INJ_CHANNEL_ENABLED */

#define ADC_MUX_SWITCH0_REG           (*(reg32 *)  ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 )
#define ADC_MUX_SWITCH0_PTR           ( (reg32 *)  ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 )

#define ADC_MUX_SWITCH_HW_CTRL_REG    (*(reg32 *)  ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL )
#define ADC_MUX_SWITCH_HW_CTRL_PTR    ( (reg32 *)  ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL )

#define ADC_PUMP_CTRL_REG             (*(reg32 *)  ADC_cy_psoc4_sar__SAR_PUMP_CTRL )
#define ADC_PUMP_CTRL_PTR             ( (reg32 *)  ADC_cy_psoc4_sar__SAR_PUMP_CTRL )

#define ADC_ANA_TRIM_REG              (*(reg32 *)  ADC_cy_psoc4_sar__SAR_ANA_TRIM )
#define ADC_ANA_TRIM_PTR              ( (reg32 *)  ADC_cy_psoc4_sar__SAR_ANA_TRIM )

#define ADC_WOUNDING_REG              (*(reg32 *)  ADC_cy_psoc4_sar__SAR_WOUNDING )
#define ADC_WOUNDING_PTR              ( (reg32 *)  ADC_cy_psoc4_sar__SAR_WOUNDING )

/**************************************
*       Register Constants
**************************************/
#define ADC_INTC_NUMBER                (ADC_IRQ__INTC_NUMBER)
#define ADC_INTC_PRIOR_NUMBER          (ADC_IRQ__INTC_PRIOR_NUM)

/* defines for CTRL register */
#define ADC_VREF_INTERNAL1024          (0x00000040Lu)
#define ADC_VREF_EXTERNAL              (0x00000050Lu)
#define ADC_VREF_VDDA_2                (0x00000060Lu)
#define ADC_VREF_VDDA                  (0x00000070Lu)
#define ADC_VREF_INTERNAL1024BYPASSED  (0x000000C0Lu)
#define ADC_VREF_VDDA_2BYPASSED        (0x000000E0Lu)
#define ADC_VREF_INTERNALVREF          (0x00000040Lu)
#define ADC_VREF_INTERNALVREFBYPASSED  (0x000000C0Lu)

#define ADC_NEG_VSSA_KELVIN            (0x00000000Lu)
#define ADC_NEG_VSSA                   (0x00000200Lu)
#define ADC_NEG_VREF                   (0x00000E00Lu)
#if(ADC_TOTAL_CHANNELS_NUM > 1u)
    #define ADC_NEG_OTHER              (uint16)((uint16)ADC_cy_psoc4_sarmux_8__VNEG0 << 9u)
#else
    #define ADC_NEG_OTHER              (0)
#endif /* ADC_TOTAL_CHANNELS_NUM > 1u */

#define ADC_SAR_HW_CTRL_NEGVREF        (0x00002000Lu)

#define ADC_BOOSTPUMP_EN               (0x00100000Lu)

#define ADC_NORMAL_PWR                 (0x00000000Lu)
#define ADC_HALF_PWR                   (0x01000000Lu)
#define ADC_MORE_PWR                   (0x02000000Lu)
#define ADC_QUARTER_PWR                (0x03000000Lu)
#define ADC_DEEPSLEEP_ON               (0x08000000Lu)

#define ADC_DSI_SYNC_CONFIG            (0x10000000Lu)
#define ADC_DSI_MODE                   (0x20000000Lu)
#define ADC_SWITCH_DISABLE             (0x40000000Lu)
#define ADC_ENABLE                     (0x80000000Lu)

/* defines for STATUS register */
#define ADC_STATUS_BUSY                (0x80000000Lu)

/* defines for SAMPLE_CTRL register */
#define ADC_ALT_RESOLUTION_10BIT       (0x00000001Lu)
#define ADC_ALT_RESOLUTION_8BIT        (0x00000000Lu)

#define ADC_DATA_ALIGN_LEFT            (0x00000002Lu)
#define ADC_DATA_ALIGN_RIGHT           (0x00000000Lu)

#define ADC_SE_SIGNED_RESULT           (0x00000004Lu)
#define ADC_SE_UNSIGNED_RESULT         (0x00000000Lu)

#define ADC_DIFF_SIGNED_RESULT         (0x00000008Lu)
#define ADC_DIFF_UNSIGNED_RESULT       (0x00000000Lu)

#define ADC_AVG_CNT_OFFSET             (4u)
#define ADC_AVG_CNT_MASK               (0x00000070Lu)
#define ADC_AVG_SHIFT                  (0x00000080Lu)

#define ADC_CONTINUOUS_EN              (0x00010000Lu)
#define ADC_DSI_TRIGGER_EN             (0x00020000Lu)
#define ADC_DSI_TRIGGER_LEVEL          (0x00040000Lu)
#define ADC_DSI_SYNC_TRIGGER           (0x00080000Lu)
#define ADC_EOS_DSI_OUT_EN             (0x80000000Lu)

/* defines for SAMPLE_TIME01 / SAMPLE_TIME23 registers */
#define ADC_SAMPLE_TIME13_OFFSET       (16u)
#define ADC_SAMPLE_TIME02_MASK         (0x000003FFLu)
#define ADC_SAMPLE_TIME13_MASK         (0x03FF0000Lu)

/* defines for RANGE_THRES registers */
#define ADC_RANGE_HIGH_OFFSET          (16u)
#define ADC_RANGE_HIGH_MASK            (0xFFFF0000Lu)
#define ADC_RANGE_LOW_MASK             (0x0000FFFFLu)

/* defines for RANGE_COND register */
/* Compare mode setting constants:
*    BELOW   - Result < Low_Limit
*    INSIDE  - Low_Limit <= Result < High_Limit
*    ABOVE   - High_Limit <= Result
*    OUTSIDE - (Result < Low_Limit) or (High_Limit <= Result)
*/
#define ADC_CMP_MODE_BELOW             (0x00000000Lu)
#define ADC_CMP_MODE_INSIDE            (0x40000000Lu)
#define ADC_CMP_MODE_ABOVE             (0x80000000Lu)
#define ADC_CMP_MODE_OUTSIDE           (0xC0000000Lu)
#define ADC_CMP_OFFSET                 (30u)

/* defines for _START_CTRL register */
#define ADC_FW_TRIGGER                 (0x00000001Lu)

/* defines for DFT_CTRL register */
#define ADC_DLY_INC                    (0x00000001Lu)
#define ADC_HIZ                        (0x00000002Lu)
#define ADC_DFT_INC_MASK               (0x000F0000Lu)
#define ADC_DFT_OUTC_MASK              (0x00700000Lu)
#define ADC_SEL_CSEL_DFT_MASK          (0x0F000000Lu)

/* configuration for clock speed > 9 Mhz based on
* characterization results
*/
#define ADC_SEL_CSEL_DFT_CHAR          (0x03000000Lu)
#define ADC_EN_CSEL_DFT                (0x10000000Lu)
#define ADC_DCEN                       (0x20000000Lu)
#define ADC_ADFT_OVERRIDE              (0x80000000Lu)

/* defines for CHAN_CONFIG / DIE_CHAN_CONFIG register
*  and channelsConfig parameter
*/
#define ADC_SARMUX_VIRT_SELECT         (0x00000070Lu)
#define ADC_DIFFERENTIAL_EN            (0x00000100Lu)
#define ADC_ALT_RESOLUTION_ON          (0x00000200Lu)
#define ADC_AVERAGING_EN               (0x00000400Lu)

#define ADC_SAMPLE_TIME_SEL_SHIFT      (12u)
#define ADC_SAMPLE_TIME_SEL_MASK       (0x00003000Lu)

#define ADC_CHANNEL_CONFIG_MASK        (0x00003700Lu)

/* for CHAN_CONFIG only */
#define ADC_DSI_OUT_EN                 (0x80000000Lu)

/* for INJ_CHAN_CONFIG only */
#define ADC_INJ_TAILGATING             (0x40000000Lu)
#define ADC_INJ_CHAN_EN                (0x80000000Lu)

/* defines for CHAN_WORK register */
#define ADC_SAR_WRK_MAX_12BIT          (0x00001000Lu)
#define ADC_SAR_WRK_MAX_10BIT          (0x00000400Lu)
#define ADC_SAR_WRK_MAX_8BIT           (0x00000100Lu)

/* defines for CHAN_RESULT register */
#define ADC_RESULT_MASK                (0x0000FFFFLu)
#define ADC_SATURATE_INTR_MIR          (0x20000000Lu)
#define ADC_RANGE_INTR_MIR             (0x40000000Lu)
#define ADC_CHAN_RESULT_VALID_MIR      (0x80000000Lu)

/* defines for INTR_MASK register */
#define ADC_EOS_MASK                   (0x00000001Lu)
#define ADC_OVERFLOW_MASK              (0x00000002Lu)
#define ADC_FW_COLLISION_MASK          (0x00000004Lu)
#define ADC_DSI_COLLISION_MASK         (0x00000008Lu)
#define ADC_INJ_EOC_MASK               (0x00000010Lu)
#define ADC_INJ_SATURATE_MASK          (0x00000020Lu)
#define ADC_INJ_RANGE_MASK             (0x00000040Lu)
#define ADC_INJ_COLLISION_MASK         (0x00000080Lu)

/* defines for INJ_RESULT register */
#define ADC_INJ_COLLISION_INTR_MIR     (0x10000000Lu)
#define ADC_INJ_SATURATE_INTR_MIR      (0x20000000Lu)
#define ADC_INJ_RANGE_INTR_MIR         (0x40000000Lu)
#define ADC_INJ_EOC_INTR_MIR           (0x80000000Lu)

/* defines for MUX_SWITCH0 register */
#define ADC_MUX_FW_VSSA_VMINUS         (0x00010000Lu)

/* defines for PUMP_CTRL register */
#define ADC_PUMP_CTRL_ENABLED          (0x80000000Lu)

/* additional defines for channelsConfig parameter */
#define ADC_IS_SATURATE_EN_MASK        (0x00000001Lu)
#define ADC_IS_RANGE_CTRL_EN_MASK      (0x00000002Lu)

/* defines for WOUNDING register */
#define ADC_WOUNDING_12BIT             (0x00000000Lu)
#define ADC_WOUNDING_10BIT             (0x00000001Lu)
#define ADC_WOUNDING_8BIT              (0x00000002Lu)

/* Trim value based on characterization */
#define ADC_TRIM_COEF                  (2u)

#if(ADC_MAX_RESOLUTION == ADC_RESOLUTION_10)
    #define ADC_ALT_WOUNDING           ADC_WOUNDING_10BIT
#else
    #define ADC_ALT_WOUNDING           ADC_WOUNDING_8BIT
#endif /* ADC_MAX_RESOLUTION == ADC_RESOLUTION_10 */

#if(ADC_DEFAULT_VREF_SEL == ADC__VDDA_2)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_VDDA_2
#elif(ADC_DEFAULT_VREF_SEL == ADC__VDDA)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_VDDA
#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_INTERNAL1024
#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024BYPASSED)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_INTERNAL1024BYPASSED
#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_INTERNALVREF
#elif(ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREFBYPASSED)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_INTERNALVREFBYPASSED
#elif(ADC_DEFAULT_VREF_SEL == ADC__VDDA_2BYPASSED)
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_VDDA_2BYPASSED
#else
    #define ADC_DEFAULT_VREF_SOURCE    ADC_VREF_EXTERNAL
#endif /* ADC_DEFAULT_VREF_SEL == ADC__VDDA_2 */

#if(ADC_DEFAULT_NEG_INPUT_SEL == ADC__VSS)
    /* Connect NEG input of SARADC to VSSA close to the SARADC for single channel mode */
    #if(ADC_TOTAL_CHANNELS_NUM == 1u)
        #define ADC_DEFAULT_SE_NEG_INPUT    ADC_NEG_VSSA
    #else
        #define ADC_DEFAULT_SE_NEG_INPUT    ADC_NEG_VSSA_KELVIN
    #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */
    /* Do not connect VSSA to VMINUS when one channel in differential mode used */
    #if((ADC_TOTAL_CHANNELS_NUM == 1u) && (ADC_CHANNELS_MODE != 0u))
        #define ADC_DEFAULT_MUX_SWITCH0     0u
    #else    /* miltiple channels or one single channel */
        #define ADC_DEFAULT_MUX_SWITCH0     ADC_MUX_FW_VSSA_VMINUS
    #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */
#elif(ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF)
    /* Do not connect VNEG to VREF when one channel in differential mode used */
    #if((ADC_TOTAL_CHANNELS_NUM == 1u) && (ADC_CHANNELS_MODE != 0u))
        #define ADC_DEFAULT_SE_NEG_INPUT    0u
    #else    /* miltiple channels or one single channel */
        #define ADC_DEFAULT_SE_NEG_INPUT    ADC_NEG_VREF
    #endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */
    #define ADC_DEFAULT_MUX_SWITCH0     0u
#elif (ADC_SINGLE_PRESENT != 0u)
    #define ADC_DEFAULT_SE_NEG_INPUT    ADC_NEG_OTHER
    #define ADC_DEFAULT_MUX_SWITCH0     0u
#else
    #define ADC_DEFAULT_SE_NEG_INPUT    0u
    #define ADC_DEFAULT_MUX_SWITCH0     0u
#endif /* ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF */

/* If the SAR is configured for multiple channels, always set SAR_HW_CTRL_NEGVREF to 1 */
#if(ADC_TOTAL_CHANNELS_NUM == 1u)
    #define ADC_DEFAULT_HW_CTRL_NEGVREF 0u
#else
    #define ADC_DEFAULT_HW_CTRL_NEGVREF ADC_SAR_HW_CTRL_NEGVREF
#endif /* (ADC_TOTAL_CHANNELS_NUM == 1u) */

#if(ADC_DEFAULT_ALT_RESOLUTION_SEL == ADC__RES8)
    #define ADC_DEFAULT_ALT_RESOLUTION     (ADC_ALT_RESOLUTION_8BIT)
    #define ADC_DEFAULT_MAX_WRK_ALT        (ADC_SAR_WRK_MAX_8BIT)
#else
    #define ADC_DEFAULT_ALT_RESOLUTION     (ADC_ALT_RESOLUTION_10BIT)
    #define ADC_DEFAULT_MAX_WRK_ALT        (ADC_SAR_WRK_MAX_10BIT)
#endif /* End ADC_DEFAULT_ALT_RESOLUTION_SEL == ADC__RES8 */

#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT)
    #define ADC_DEFAULT_JUSTIFICATION  ADC_DATA_ALIGN_RIGHT
#else
    #define ADC_DEFAULT_JUSTIFICATION  ADC_DATA_ALIGN_LEFT
#endif /* ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */

#if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FSIGNED)
    #define ADC_DEFAULT_DIFF_RESULT_FORMAT ADC_DIFF_SIGNED_RESULT
#else
    #define ADC_DEFAULT_DIFF_RESULT_FORMAT ADC_DIFF_UNSIGNED_RESULT
#endif /* ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FSIGNED */

#if(ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED)
    #define ADC_DEFAULT_SE_RESULT_FORMAT ADC_SE_SIGNED_RESULT
#else
    #define ADC_DEFAULT_SE_RESULT_FORMAT ADC_SE_UNSIGNED_RESULT
#endif /* ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */

#if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING)
    #define ADC_DSI_TRIGGER        0u
#else /* Firmware trigger */
    #define ADC_DSI_TRIGGER        (ADC_DSI_TRIGGER_EN | ADC_DSI_SYNC_TRIGGER)
#endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */

#if(ADC_INJ_CHANNEL_ENABLED)
    #define ADC_SAR_INTR_MASK      (ADC_EOS_MASK | ADC_INJ_EOC_MASK)
#else
    #define ADC_SAR_INTR_MASK      (ADC_EOS_MASK)
#endif /* ADC_INJ_CHANNEL_ENABLED*/

#if(ADC_DEFAULT_AVG_MODE == ADC__FIXEDRESOLUTION)
    #define ADC_AVG_SHIFT_MODE     ADC_AVG_SHIFT
#else
    #define ADC_AVG_SHIFT_MODE     0u
#endif /* End ADC_DEFAULT_AVG_MODE */

#define ADC_COMPARE_MODE           (uint32)((uint32)(ADC_DEFAULT_COMPARE_MODE) \
                                                << ADC_CMP_OFFSET)

#if(ADC_TOTAL_CHANNELS_NUM > 1u)
    #define ADC_DEFAULT_SWITCH_CONF    0u
#else /* Disable SAR sequencer from enabling routing switches in single channel mode */
    #define ADC_DEFAULT_SWITCH_CONF    ADC_SWITCH_DISABLE
#endif /* End ADC_TOTAL_CHANNELS_NUM > 1 */

#define ADC_DEFAULT_POWER \
       ((ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 4)) ? ADC_NORMAL_PWR : \
       ((ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 8)) ? ADC_HALF_PWR : \
                                                                                       ADC_QUARTER_PWR))

#define ADC_DEFAULT_CTRL_REG_CFG       (ADC_DEFAULT_VREF_SOURCE \
                                                   | ADC_DEFAULT_SE_NEG_INPUT \
                                                   | ADC_DEFAULT_HW_CTRL_NEGVREF \
                                                   | ADC_DEFAULT_POWER \
                                                   | ADC_DSI_SYNC_CONFIG \
                                                   | ADC_DEFAULT_SWITCH_CONF)

#define ADC_DEFAULT_SAMPLE_CTRL_REG_CFG (ADC_DEFAULT_DIFF_RESULT_FORMAT \
                                                    | ADC_DEFAULT_SE_RESULT_FORMAT \
                                                    | ADC_DEFAULT_JUSTIFICATION \
                                                    | ADC_DEFAULT_ALT_RESOLUTION \
                                           | (uint8)(ADC_DEFAULT_AVG_SAMPLES_NUM \
                                                   << ADC_AVG_CNT_OFFSET) \
                                                    | ADC_AVG_SHIFT_MODE \
                                                    | ADC_DSI_TRIGGER \
                                                    | ADC_EOS_DSI_OUT_EN)

#define ADC_DEFAULT_RANGE_THRES_REG_CFG (ADC_DEFAULT_LOW_LIMIT \
            | (uint32)((uint32)ADC_DEFAULT_HIGH_LIMIT << ADC_RANGE_HIGH_OFFSET))

#define ADC_DEFAULT_SAMPLE_TIME01_REG_CFG (ADC_DEFAULT_ACLKS_NUM \
            | (uint32)((uint32)ADC_DEFAULT_BCLKS_NUM << ADC_SAMPLE_TIME13_OFFSET))

#define ADC_DEFAULT_SAMPLE_TIME23_REG_CFG (ADC_DEFAULT_CCLKS_NUM \
            | (uint32)((uint32)ADC_DEFAULT_DCLKS_NUM << ADC_SAMPLE_TIME13_OFFSET))

#endif /* End CY_ADC_SAR_SEQ_ADC_H */

/* [] END OF FILE */

and

/*******************************************************************************
* File Name: ADC.c
* Version 2.50
*
* Description:
*  This file provides the source code to the API for the Sequencing Successive
*  Approximation ADC Component Component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2017, Cypress Semiconductor Corporation.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#include "ADC.h"

/***************************************
* Global data allocation
***************************************/
uint8 ADC_initVar = 0u;
volatile int16 ADC_offset[ADC_TOTAL_CHANNELS_NUM];
volatile int32 ADC_countsPer10Volt[ADC_TOTAL_CHANNELS_NUM];   /* Gain compensation */

/***************************************
* Local data allocation
***************************************/
/* Channels configuration generated by customiser */
static const uint32 CYCODE ADC_channelsConfig[] = { 0x00000400u, 0x00000500u, 0x00001400u, 0x00001400u, 0x00000000u };

/*******************************************************************************
* Function Name: ADC_Start
********************************************************************************
*
* Summary:
*  Performs all required initialization for this component
*  and enables the power. The power will be set to the appropriate
*  power based on the clock frequency.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Global variables:
*  The ADC_initVar variable is used to indicate when/if initial
*  configuration of this component has happened. The variable is initialized to
*  zero and set to 1 the first time ADC_Start() is called. This allows for
*  component Re-Start without re-initialization in all subsequent calls to the
*  ADC_Start() routine.
*  If re-initialization of the component is required the variable should be set
*  to zero before call of ADC_Start() routine, or the user may call
*  ADC_Init() and ADC_Enable() as done in the
*  ADC_Start() routine.
*
*******************************************************************************/
void ADC_Start(void)
{
    /* If not Initialized then initialize all required hardware and software */
    if(ADC_initVar == 0u)
    {
        ADC_Init();
        ADC_initVar = 1u;
    }
    ADC_Enable();
}

/*******************************************************************************
* Function Name: ADC_Init
********************************************************************************
*
* Summary:
*  Initialize component's parameters to the parameters set by user in the
*  customizer of the component placed onto schematic. Usually called in
*  ADC_Start().
*
* Parameters:
*  None.
*
* Return:
*  None.
*
* Global variables:
*  The ADC_offset variable is initialized.
*
*******************************************************************************/
void ADC_Init(void)
{
    uint32 chNum;
    uint32 tmpRegVal;
    int32 counts;

    #if(ADC_TOTAL_CHANNELS_NUM > 1u)
        static const uint8 CYCODE ADC_InputsPlacement[] =
        {
            (uint8)(ADC_cy_psoc4_sarmux_8__CH_0_PORT << 4u) |
            (uint8)ADC_cy_psoc4_sarmux_8__CH_0_PIN
            ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_1_PORT << 4u) |
             (uint8)ADC_cy_psoc4_sarmux_8__CH_1_PIN
            #if(ADC_TOTAL_CHANNELS_NUM > 2u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_2_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_2_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 2u */
            #if(ADC_TOTAL_CHANNELS_NUM > 3u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_3_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_3_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 3u */
            #if(ADC_TOTAL_CHANNELS_NUM > 4u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_4_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_4_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 4u */
            #if(ADC_TOTAL_CHANNELS_NUM > 5u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_5_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_5_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 5u */
            #if(ADC_TOTAL_CHANNELS_NUM > 6u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_6_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_6_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 6u */
            #if(ADC_TOTAL_CHANNELS_NUM > 7u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_7_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_7_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 7u */
            #if(ADC_TOTAL_CHANNELS_NUM > 8u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_8_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_8_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 8u */
            #if(ADC_TOTAL_CHANNELS_NUM > 9u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_9_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_9_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 9u */
            #if(ADC_TOTAL_CHANNELS_NUM > 10u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_10_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_10_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 10u */
            #if(ADC_TOTAL_CHANNELS_NUM > 11u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_11_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_11_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 11u */
            #if(ADC_TOTAL_CHANNELS_NUM > 12u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_12_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_12_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 12u */
            #if(ADC_TOTAL_CHANNELS_NUM > 13u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_13_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_13_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 13u */
            #if(ADC_TOTAL_CHANNELS_NUM > 14u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_14_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_14_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 14u */
            #if(ADC_TOTAL_CHANNELS_NUM > 15u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_15_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_15_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 15u */
            #if(ADC_TOTAL_CHANNELS_NUM > 16u)
                ,(uint8)(ADC_cy_psoc4_sarmux_8__CH_16_PORT << 4u) |
                 (uint8)ADC_cy_psoc4_sarmux_8__CH_16_PIN
            #endif /* End ADC_TOTAL_CHANNELS_NUM > 16u */
        };
    #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */

    #if(ADC_IRQ_REMOVE == 0u)
        /* Start and set interrupt vector */
        CyIntSetPriority(ADC_INTC_NUMBER, ADC_INTC_PRIOR_NUMBER);
        (void)CyIntSetVector(ADC_INTC_NUMBER, &ADC_ISR);
    #endif   /* End ADC_IRQ_REMOVE */

    /* Init SAR and MUX registers */
    ADC_SAR_CHAN_EN_REG = ADC_DEFAULT_EN_CHANNELS;
    ADC_SAR_CTRL_REG |= ADC_DEFAULT_CTRL_REG_CFG | 
        /* Enable the SAR internal pump when global pump is enabled */
        (((ADC_PUMP_CTRL_REG & ADC_PUMP_CTRL_ENABLED) != 0u) ? 
        ADC_BOOSTPUMP_EN : 0u);
    ADC_SAR_SAMPLE_CTRL_REG = ADC_DEFAULT_SAMPLE_CTRL_REG_CFG;
    ADC_SAR_RANGE_THRES_REG = ADC_DEFAULT_RANGE_THRES_REG_CFG;
    ADC_SAR_RANGE_COND_REG  = ADC_COMPARE_MODE;
    ADC_SAR_SAMPLE_TIME01_REG = ADC_DEFAULT_SAMPLE_TIME01_REG_CFG;
    ADC_SAR_SAMPLE_TIME23_REG = ADC_DEFAULT_SAMPLE_TIME23_REG_CFG;

    /* Connect Vm to VSSA when even one channel is single-ended or multiple channels configured */
    #if(ADC_DEFAULT_MUX_SWITCH0 != 0u)
        ADC_MUX_SWITCH0_REG |= ADC_DEFAULT_MUX_SWITCH0;
        /* Set MUX_HW_CTRL_VSSA in MUX_SWITCH_HW_CTRL when multiple channels enabled */
        #if(ADC_TOTAL_CHANNELS_NUM > 1u)
            ADC_MUX_SWITCH_HW_CTRL_REG |= ADC_DEFAULT_MUX_SWITCH0;
        #endif /* ADC_TOTAL_CHANNELS_NUM > 1u */
    #endif /*ADC_CHANNELS_MODE !=0 */

    ADC_SAR_SATURATE_INTR_MASK_REG = 0u;
    ADC_SAR_RANGE_INTR_MASK_REG = 0u;
    ADC_SAR_INTR_MASK_REG = ADC_SAR_INTR_MASK;

    #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0)
        ADC_ANA_TRIM_REG = ADC_TRIM_COEF;
    #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */

    /* Read and modify default configuration based on characterization */
    tmpRegVal = ADC_SAR_DFT_CTRL_REG;
    tmpRegVal &= (uint32)~ADC_DCEN;

    #if(ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0)
        #if(ADC_NOMINAL_CLOCK_FREQ > (ADC_MAX_FREQUENCY / 2))
            tmpRegVal |= ADC_SEL_CSEL_DFT_CHAR;
        #else  /* clock speed < 9 Mhz */
            tmpRegVal |= ADC_DLY_INC;
        #endif /* clock speed > 9 Mhz */
    #else
        #if ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \
             (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF))
            tmpRegVal |= ADC_DLY_INC;
        #else
            tmpRegVal |= ADC_DCEN;
            tmpRegVal &= (uint32)~ADC_DLY_INC;
        #endif /* ((ADC_DEFAULT_VREF_SEL == ADC__INTERNAL1024) || \
                   (ADC_DEFAULT_VREF_SEL == ADC__INTERNALVREF)) */
    #endif /* (ADC_CY_SAR_IP_VER == ADC_CY_SAR_IP_VER0) */

    ADC_SAR_DFT_CTRL_REG = tmpRegVal;

    #if(ADC_MAX_RESOLUTION != ADC_RESOLUTION_12)
        ADC_WOUNDING_REG = ADC_ALT_WOUNDING;
    #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */

    for(chNum = 0u; chNum < ADC_TOTAL_CHANNELS_NUM; chNum++)
    {
        tmpRegVal = (ADC_channelsConfig[chNum] & ADC_CHANNEL_CONFIG_MASK);
        #if(ADC_TOTAL_CHANNELS_NUM > 1u)
            tmpRegVal |= ADC_InputsPlacement[chNum];
        #endif /* End ADC_TOTAL_CHANNELS_NUM > 1u */

        /* When the part is limited to 10-bit then the SUB_RESOLUTION bit
        *  will be ignored and the RESOLUTION bit selects between 10-bit
        *  (0) and 8-bit (1) resolution.
        */
        #if((ADC_MAX_RESOLUTION != ADC_RESOLUTION_12) && \
            (ADC_ALT_WOUNDING == ADC_WOUNDING_10BIT))
            tmpRegVal &= (uint32)(~ADC_ALT_RESOLUTION_ON);
        #endif /* ADC_MAX_RESOLUTION != ADC_RESOLUTION_12 */

        #if(ADC_INJ_CHANNEL_ENABLED)
        if(chNum < ADC_SEQUENCED_CHANNELS_NUM)
        #endif /* ADC_INJ_CHANNEL_ENABLED */
        {
            CY_SET_REG32((reg32 *)(ADC_SAR_CHAN_CONFIG_IND + (uint32)(chNum << 2)), tmpRegVal);

            if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u)
            {
                ADC_SAR_SATURATE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum);
            }

            if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u)
            {
                ADC_SAR_RANGE_INTR_MASK_REG |= (uint16)((uint16)1 << chNum);
            }
        }
        #if(ADC_INJ_CHANNEL_ENABLED)
            else
            {
                CY_SET_REG32(ADC_SAR_INJ_CHAN_CONFIG_PTR, tmpRegVal | ADC_INJ_TAILGATING);

                if((ADC_channelsConfig[chNum] & ADC_IS_SATURATE_EN_MASK) != 0u)
                {
                    ADC_SAR_INTR_MASK_REG |= ADC_INJ_SATURATE_MASK;
                }

                if((ADC_channelsConfig[chNum] & ADC_IS_RANGE_CTRL_EN_MASK) != 0u)
                {
                    ADC_SAR_INTR_MASK_REG |= ADC_INJ_RANGE_MASK;
                }
            }
        #endif /* ADC_INJ_CHANNEL_ENABLED */

        if((ADC_channelsConfig[chNum] & ADC_ALT_RESOLUTION_ON) != 0u)
        {
               counts = (int32)ADC_DEFAULT_MAX_WRK_ALT;
        }
        else
        {
               counts = (int32)ADC_SAR_WRK_MAX_12BIT;
        }

        if((ADC_channelsConfig[chNum] & ADC_DIFFERENTIAL_EN) == 0u)
        {
            #if((ADC_DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED) && \
                (ADC_DEFAULT_NEG_INPUT_SEL == ADC__VREF))
                /* Set offset to the minus half scale to convert results to unsigned format */
                ADC_offset[chNum] = (int16)(counts / -2);
            #else
                ADC_offset[chNum] = 0;
            #endif /* end DEFAULT_SE_RESULT_FORMAT_SEL == ADC__FSIGNED */
        }
        else    /* Differential channel */
        {
            #if(ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED)
                /* Set offset to the half scale to convert results to signed format */
                ADC_offset[chNum] = (int16)(counts / 2);
            #else
                ADC_offset[chNum] = 0;
            #endif /* end ADC_DEFAULT_DIFF_RESULT_FORMAT_SEL == ADC__FUNSIGNED */
        }
        /* Calculate gain in counts per 10 volts with rounding */
        ADC_countsPer10Volt[chNum] = (int16)(((counts * ADC_10MV_COUNTS) +
                            ADC_DEFAULT_VREF_MV_VALUE) / (ADC_DEFAULT_VREF_MV_VALUE * 2));
    }
}

/*******************************************************************************
* Function Name: ADC_SAR_1_Enable
********************************************************************************
*
* Summary:
*  Enables the clock and analog power for SAR ADC.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_Enable(void)
{
    if (0u == (ADC_SAR_CTRL_REG & ADC_ENABLE))
    {
        #if(ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0)

            while (0u != (ADC_SAR_STATUS_REG & ADC_STATUS_BUSY))
            {
                /* wait for SAR to go idle to avoid deadlock */
            }
        #endif /* (ADC_CY_SAR_IP_VER != ADC_CY_SAR_IP_VER0) */

        ADC_SAR_CTRL_REG |= ADC_ENABLE;

        /* The block is ready to use 10 us after the enable signal is set high. */
        CyDelayUs(ADC_10US_DELAY);         
    }
}

/*******************************************************************************
* Function Name: ADC_Stop
********************************************************************************
*
* Summary:
*  This function stops ADC conversions and puts the ADC into its lowest power
*  mode.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_Stop(void)
{
    ADC_SAR_CTRL_REG &= (uint32)~ADC_ENABLE;
}

/*******************************************************************************
* Function Name: ADC_StartConvert
********************************************************************************
*
* Summary:
*  Description:
*  For free running mode, this API starts the conversion process and it
*  runs continuously.
*
*  In a triggered mode, this routine triggers every conversion by
*  writing into the FW_TRIGGER bit in SAR_START_CTRL reg. In triggered mode,
*  every conversion has to start by this API.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_StartConvert(void)
{
    #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING)
        ADC_SAR_SAMPLE_CTRL_REG |= ADC_CONTINUOUS_EN;
    #else /* Firmware trigger */
        ADC_SAR_START_CTRL_REG = ADC_FW_TRIGGER;
    #endif /* End ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */

}

/*******************************************************************************
* Function Name: ADC_StopConvert
********************************************************************************
*
* Summary:
*  Forces the ADC to stop all conversions.
*
* Parameters:
*  None.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_StopConvert(void)
{
    #if(ADC_DEFAULT_SAMPLE_MODE_SEL == ADC__FREERUNNING)
        ADC_SAR_SAMPLE_CTRL_REG &= (uint32)(~ADC_CONTINUOUS_EN);
    #endif /* ADC_DEFAULT_SAMPLE_MODE == ADC__FREERUNNING */
}

/*******************************************************************************
* Function Name: ADC_IsEndConversion
********************************************************************************
*
* Summary:
*  Description: Checks for ADC end of conversion for the case one
*  channel and end of scan for the case of multiple channels. It acts
*  as a software version of the EOC. This function provides the
*  programmer with two options. In one mode this function
*  immediately returns with the conversion status. In the other mode,
*  the function does not return (blocking) until the conversion has
*  completed.
*
* Parameters:
*  ADC_RETURN_STATUS        -> Immediately returns conversion result status
*  ADC_WAIT_FOR_RESULT      -> Does not return until ADC complete
*  ADC_RETURN_STATUS_INJ    -> Immediately returns conversion result status
*                              for injection channel
*  ADC_WAIT_FOR_RESULT_INJ  -> Does not return until ADC completes injection
*                              channel conversion
*
* Return:
*  If a non-zero value is returned, the last conversion or scan has completed.
*  If the returned value is zero, the ADC is still in the process of a scan.
*
*******************************************************************************/
uint32 ADC_IsEndConversion(uint32 retMode)
{
    uint32 status = 0u;

    if((retMode & (ADC_RETURN_STATUS | ADC_WAIT_FOR_RESULT)) != 0u)
    {
        do
        {
            status = ADC_SAR_INTR_REG & ADC_EOS_MASK;
        }while((status == 0u) && ((retMode & ADC_WAIT_FOR_RESULT) != 0u));

        if(status != 0u)
        {
            /* Clear EOS bit */
            ADC_SAR_INTR_REG = ADC_EOS_MASK;
        }
    }

    #if(ADC_INJ_CHANNEL_ENABLED)
        if((retMode & (ADC_RETURN_STATUS_INJ | ADC_WAIT_FOR_RESULT_INJ)) != 0u)
        {
            do
            {
                status |= ADC_SAR_INTR_REG & ADC_INJ_EOC_MASK;
            }while(((status & ADC_INJ_EOC_MASK) == 0u) &&
                   ((retMode & ADC_WAIT_FOR_RESULT_INJ) != 0u));

            if((status & ADC_INJ_EOC_MASK) != 0u)
            {
                /* Clear Injection EOS bit */
                ADC_SAR_INTR_REG = ADC_INJ_EOC_MASK;
            }
        }
    #endif /* ADC_INJ_CHANNEL_ENABLED */

    return (status);
}

/*******************************************************************************
* Function Name: ADC_GetResult16
********************************************************************************
*
* Summary:
*  Gets the data available in the SAR DATA register.
*
* Parameters:
*  chan: The ADC channel in which to return the result. The first channel
*  is 0 and the injection channel if enabled is the number of valid channels.
*
* Return:
*  Returns converted data as a signed 16-bit integer
*
*******************************************************************************/
int16 ADC_GetResult16(uint32 chan)
{
    uint32 result;

    /* Halt CPU in debug mode if channel is out of valid range */
    CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM);

    if(chan < ADC_SEQUENCED_CHANNELS_NUM)
    {
        result = CY_GET_REG32((reg32 *)(ADC_SAR_CHAN_RESULT_IND + (uint32)(chan << 2u))) &
                ADC_RESULT_MASK;
    }
    else
    {
        #if(ADC_INJ_CHANNEL_ENABLED)
            result = ADC_SAR_INJ_RESULT_REG & ADC_RESULT_MASK;
        #else
            result = 0u;
        #endif /* ADC_INJ_CHANNEL_ENABLED */
    }

    return ( (int16)result );
}

/*******************************************************************************
* Function Name: ADC_SetChanMask
********************************************************************************
*
* Summary:
*  Sets the channel enable mask.
*
* Parameters:
*  mask: Sets which channels that will be
*  scanned. Setting bits for channels that do not exist will have no
*  effect. For example, if only 6 channels were enabled, setting a
*  mask of 0x0103 would only enable the last two channels (0 and 1).
*  This API will not enable the injection channel.
*  Examples: If the component is setup to sequence through 8
*  channels, a mask of 0x000F would enable channels 0, 1, 2, and 3.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_SetChanMask(uint32 mask)
{
    ADC_SAR_CHAN_EN_REG = mask & ADC_MAX_CHANNELS_EN_MASK;
}

#if(ADC_INJ_CHANNEL_ENABLED)

    /*******************************************************************************
    * Function Name: ADC_EnableInjection
    ********************************************************************************
    *
    * Summary:
    *  Enables the injection channel for the next scan only.
    *
    * Parameters:
    *  None.
    *
    * Return:
    *  None.
    *
    *******************************************************************************/
    void ADC_EnableInjection(void)
    {
        ADC_SAR_INJ_CHAN_CONFIG_REG |= ADC_INJ_CHAN_EN;
    }

#endif /* ADC_INJ_CHANNEL_ENABLED */

/*******************************************************************************
* Function Name: ADC_SetLowLimit
********************************************************************************
*
* Summary:
*  Sets the low limit parameter for a limit condition.
*
* Parameters:
*  lowLimit: The low limit for a limit condition.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_SetLowLimit(uint32 lowLimit)
{
    ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_LOW_MASK);
    ADC_SAR_RANGE_THRES_REG |= lowLimit & ADC_RANGE_LOW_MASK;
}

/*******************************************************************************
* Function Name: ADC_SetHighLimit
********************************************************************************
*
* Summary:
*  Sets the low limit parameter for a limit condition.
*
* Parameters:
*  highLimit: The high limit for a limit condition.
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_SetHighLimit(uint32 highLimit)
{
    ADC_SAR_RANGE_THRES_REG &= (uint32)(~ADC_RANGE_HIGH_MASK);
    ADC_SAR_RANGE_THRES_REG |= (uint32)(highLimit << ADC_RANGE_HIGH_OFFSET);
}

/*******************************************************************************
* Function Name: ADC_SetLimitMask
********************************************************************************
*
* Summary:
*  Sets the channel limit condition mask.
*
* Parameters:
*  mask: Sets which channels that may cause a
*  limit condition interrupt. Setting bits for channels that do not exist
*  will have no effect. For example, if only 6 channels were enabled,
*  setting a mask of 0x0103 would only enable the last two channels (0 and 1).
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_SetLimitMask(uint32 mask)
{
    ADC_SAR_RANGE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK;
}

/*******************************************************************************
* Function Name: ADC_SetSatMask
********************************************************************************
*
* Summary:
*  Sets the channel saturation event mask.
*
* Parameters:
*  mask: Sets which channels that may cause a
*  saturation event interrupt. Setting bits for channels that do not exist
*  will have no effect. For example, if only 8 channels were enabled,
*  setting a mask of 0x01C0 would only enable two channels (6 and 7).
*
* Return:
*  None.
*
*******************************************************************************/
void ADC_SetSatMask(uint32 mask)
{
    ADC_SAR_SATURATE_INTR_MASK_REG = mask & ADC_MAX_CHANNELS_EN_MASK;
}

/*******************************************************************************
* Function Name: ADC_SetOffset
********************************************************************************
*
* Summary:
*   Description: Sets the ADC offset which is used by the functions
*   ADC_CountsTo_uVolts, ADC_CountsTo_mVolts and ADC_CountsTo_Volts
*   to substract the offset from the given reading
*   before calculating the voltage conversion.
*
* Parameters:
*  chan: ADC channel number.
*  offset: This value is a measured value when the
*          inputs are shorted or connected to the same input voltage.
*
* Return:
*  None.
*
* Global variables:
*  ADC_Offset:  Modified to set the user provided offset.
*
*******************************************************************************/
void ADC_SetOffset(uint32 chan, int16 offset)
{
    /* Halt CPU in debug mode if channel is out of valid range */
    CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM);

    ADC_offset[chan] = offset;
}

/*******************************************************************************
* Function Name: ADC_SetGain
********************************************************************************
*
* Summary:
*  Description: Sets the ADC gain in counts per 10 volt for the voltage
*  conversion functions below. This value is set by default by the
*  reference and input range settings. It should only be used to further
*  calibrate the ADC with a known input or if an external reference is
*  used. Affects the ADC_CountsTo_uVolts, ADC_CountsTo_mVolts
*  and ADC_CountsTo_Volts functions by supplying the correct
*  conversion between ADC counts and voltage.
*
* Parameters:
*  chan: ADC channel number.
*  adcGain: ADC gain in counts per 10 volts.
*
* Return:
*  None.
*
* Global variables:
*  ADC_CountsPer10Volt:  modified to set the ADC gain in counts
*   per 10 volt.
*
*******************************************************************************/
void ADC_SetGain(uint32 chan, int32 adcGain)
{
    /* Halt CPU in debug mode if channel is out of valid range */
    CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM);

    ADC_countsPer10Volt[chan] = adcGain;
}

#if(ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT)

    /*******************************************************************************
    * Function Name: ADC_CountsTo_mVolts
    ********************************************************************************
    *
    * Summary:
    *  This function converts ADC counts to mVolts
    *  This function is not available when left data format justification selected.
    *
    * Parameters:
    *  chan: The ADC channel number.
    *  adcCounts: Result from the ADC conversion
    *
    * Return:
    *  Results in mVolts
    *
    * Global variables:
    *  ADC_countsPer10Volt:  used to convert ADC counts to mVolts.
    *  ADC_Offset:  Used as the offset while converting ADC counts
    *   to mVolts.
    *
    *******************************************************************************/
    int16 ADC_CountsTo_mVolts(uint32 chan, int16 adcCounts)
    {
        int16 mVolts;

        /* Halt CPU in debug mode if channel is out of valid range */
        CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM);

        /* Divide the adcCount when accumulate averaging mode selected */
        #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE)
            if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u)
            {
                adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV;
            }
        #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */

        /* Subtract ADC offset */
        adcCounts -= ADC_offset[chan];

        mVolts = (int16)((((int32)adcCounts * ADC_10MV_COUNTS) + ( (adcCounts > 0) ?
                 (ADC_countsPer10Volt[chan] / 2) : (-(ADC_countsPer10Volt[chan] / 2)) ))
                 / ADC_countsPer10Volt[chan]);

        return( mVolts );
    }

    /*******************************************************************************
    * Function Name: ADC_CountsTo_uVolts
    ********************************************************************************
    *
    * Summary:
    *  This function converts ADC counts to micro Volts
    *  This function is not available when left data format justification selected.
    *
    * Parameters:
    *  chan: The ADC channel number.
    *  adcCounts: Result from the ADC conversion
    *
    * Return:
    *  Results in uVolts
    *
    * Global variables:
    *  ADC_countsPer10Volt:  used to convert ADC counts to uVolts.
    *  ADC_Offset:  Used as the offset while converting ADC counts
    *   to mVolts.
    *
    * Theory:
    *  Care must be taken to not exceed the maximum value for a 31 bit signed
    *  number in the conversion to uVolts and at the same time not loose
    *  resolution.
    *  To convert adcCounts to microVolts it is required to be multiplied
    *  on 10 million and later divide on gain in counts per 10V.
    *
    *******************************************************************************/
    int32 ADC_CountsTo_uVolts(uint32 chan, int16 adcCounts)
    {
        int64 uVolts;

        /* Halt CPU in debug mode if channel is out of valid range */
        CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM);

        /* Divide the adcCount when accumulate averaging mode selected */
        #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE)
            if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u)
            {
                adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV;
            }
        #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */

        /* Subtract ADC offset */
        adcCounts -= ADC_offset[chan];

        uVolts = ((int64)adcCounts * ADC_10UV_COUNTS) / ADC_countsPer10Volt[chan];

        return( (int32)uVolts );
    }

    /*******************************************************************************
    * Function Name: ADC_CountsTo_Volts
    ********************************************************************************
    *
    * Summary:
    *  Converts the ADC output to Volts as a floating point number.
    *  This function is not available when left data format justification selected.
    *
    * Parameters:
    *  chan: The ADC channel number.
    *  Result from the ADC conversion
    *
    * Return:
    *  Results in Volts
    *
    * Global variables:
    *  ADC_countsPer10Volt:  used to convert ADC counts to Volts.
    *  ADC_Offset:  Used as the offset while converting ADC counts
    *   to mVolts.
    *
    *******************************************************************************/
    float32 ADC_CountsTo_Volts(uint32 chan, int16 adcCounts)
    {
        float32 volts;

        /* Halt CPU in debug mode if channel is out of valid range */
        CYASSERT(chan < ADC_TOTAL_CHANNELS_NUM);

        /* Divide the adcCount when accumulate averaging mode selected */
        #if(ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE)
            if((ADC_channelsConfig[chan] & ADC_AVERAGING_EN) != 0u)
            {
                adcCounts /= ADC_DEFAULT_AVG_SAMPLES_DIV;
            }
        #endif /* ADC_DEFAULT_AVG_MODE == ADC__ACCUMULATE */

        /* Subtract ADC offset */
        adcCounts -= ADC_offset[chan];

        volts = ((float32)adcCounts * ADC_10V_COUNTS) / (float32)ADC_countsPer10Volt[chan];

        return( volts );
    }

#endif /* End ADC_DEFAULT_JUSTIFICATION_SEL == ADC__RIGHT */

/* [] END OF FILE */

Big files.... let me know what adding those 4 files does

tkrahn commented 2 years ago

Holy guacamole! 1594 lines of code, just to read the temperature :) I'm a little worried that this will completely exhaust the memory resources of the small micro controller and we may have conflicts with the existing ADC code. Yet most of it are definitions of constants that hopefully get eliminated during compiler optimizations. Therefore I'm going to try it.

Mr-HaleYa commented 2 years ago

Lol yes, that is a ton of code! It should not exahst the SoC as it is the code that the manufacturer recommends, and It looks like 90% of it is just declarations. Let me know how it goes 😃

sysfu commented 1 year ago

Holy guacamole! 1594 lines of code, just to read the temperature :) I'm a little worried that this will completely exhaust the memory resources of the small micro controller and we may have conflicts with the existing ADC code. Yet most of it are definitions of constants that hopefully get eliminated during compiler optimizations. Therefore I'm going to try it.

Were you successful in getting your code to compile and yield live temperature readings? I'm thinking about doing something similar with a Heltec CubeCell-GPS board.