Usage of undocumented performance events on Haswell

[hadibrais]

Quartz uses the two encodings 0x530cd3 and 0x5303d3 for the events MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM and MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM, respectively. However, these encodings are only documented in the Intel manual for Ivy Bridge and not Haswell. Instead, on Haswell, the encodings to be used should be 0x5304d3 and 0x5301d3, respectively.

[Gumi-presentation-by-Dzh]

Sorry to bored you, but where do you find this events code? Are there others events code we can use?

Just like

define FOREACH_PMC_HW_EVENT(ACTION) \

ACTION("CYCLE_ACTIVITY:STALLS_L2_PENDING", NULL, 0x55305a3) \ ACTION("MEM_LOAD_UOPS_L3_HIT_RETIRED:XSNP_NONE", NULL, 0x5308d2) \ ACTION("MEM_LOAD_UOPS_L3_MISS_RETIRED:REMOTE_DRAM", NULL, 0x530cd3) \ ACTION("MEM_LOAD_UOPS_L3_MISS_RETIRED:LOCAL_DRAM", NULL, 0x5303d3)

[hadibrais]

The event codes are the values written into the PERFEVTSEL registers. Refer to the Intel manual V3 Chapter 18 and 19.

[Gumi-presentation-by-Dzh]

I got the event num and umask value in Chapter 19, How can I construct event address？ By the way, How did you calculate 0x5304d3 instead of 0x530cd3? Sorry, I am not familiar with the address construction of counter events or perf events.

[hadibrais]

Please ask such questions on Stack Overflow, not here, because they are not really specific to Quartz per se. They are also not related to this issue that I've opened.

[Gumi-presentation-by-Dzh]

Thanks a lot.

[Gumi-presentation-by-Dzh]

But I still work well with Quartz on Haswell (even in Broadwell) with 0x530cd3 and 0x5303d3 for the events , so I just puzzle about the event code 0x5304d3 and 0x5301d3 you provide. How are these event codes accurately calculated, and what are the event code, masks and counters? Does Quartz provide the wrong event code in Haswell(v3) (or Broadwell(v4))?