hadibrais
commented
6 years ago You need to modify the following existing files to add support for a new microarchitecture: cpu.h, cpu.c, known_cpus.h, and xeon-ex.h. In addition, you have to add a new file called skylake.h that is similar to the header files of other microarchitectures.
The event codes are the values written into the PERFEVTSEL registers. Each byte of the value 0x55305a3 specifies some part of the event. Refer to the Intel manual V3 Chapter 18 and 19 for more information on the format of PERFEVTSEL.
I think that the two events CYCLE_ACTIVITY:STALLS_L2_PENDING and CYCLE_ACTIVITY:STALLS_L2_MISS represent the same thin. Although it's not clear whether L1 prefetcher requests are counted by any of these events. This issue exists with all microarchitectures though.
You can also make use of the event CYCLE_ACTIVITY.STALLS_L3_MISS, which is new in Skylake to improve the accuracy of calculating the number of cycles to inject.
kjhnet
Hi, I'm trying to get quartz to work on Skylake cpus. According to the paper, LDM_STALL is derived from L2stalls, L3 hits L3 miss.. which in turn are derived from the performance counter events on different cpu micro-architecture. I looked up(with papi_native_avail command) the events used on Haswell and found that most of the events still exist on Skylake except CYCLE_ACTIVITY:STALLS_L2_PENDING. The closest event I know is CYCLE_ACTIVITY:STALLS_L2_MISS which counts the Execution stalls while at least one L2 demand load is outstanding . But I'm not sure. So any idea on Skylake which event is equivalent?
By the way, I'm tyring to access native event counter instead of PAPI for performance reasons. So I have to assemble integer format of event id similar to the number 0x55305a3 in here. Any useful references for how this event id is represented?