Support SystemVerilog and Verilog

[mattyoung101]

This PR adds some support for Verilog and SystemVerilog, both of which are covered by the same Treesitter grammar in Neovim.

begin and end blocks should be coloured correctly, which are the main blocks in both languages. I've included support for some extra things like bit indexes. Unfortunately, the SystemVerilog grammar is not very reliable at the moment, which can sometimes cause issues with highlighting. I was also unable to get nested expressions like (a+(a+b)) to highlight fully correctly.

[HiPhish]

Thank you, but I don't think keyword delimiters like begin/end should be part of the default query. I already mentioned this in PR #3, but I prefer rainbow-delimiters to be parentheses only and rainbow-blocks to be parentheses and keyword-like delimiters. I have already done the same for Lua if you want to see it for reference.

The reason for this is that if we highlight entire words the text can become too vibrant and exhausting to look at. So I prefer the default query to be more conservative. The only exception are languages like HTML where entire words delimiters are the only delimiters, so it doesn't make sense to have any other default query. I should probably write this down in the CONTRIBUTING file.

[mattyoung101]

Thanks for the feedback! I will update the PR accordingly.

[HiPhish]

You even updated the documentation, thank you. But there are a number of patterns which have no corresponding code in the test file:

• data_type
• named_port_connection
• named_parameter_assignment
• hierarchical_instance
• parameter_value_assignment
• cast

The following patterns use the wrong capture groups (@begin/@end instead of @opening/@closing):

• event_control
• primary

And finally, I found this node type that has no pattern: constant_primary.

[mattyoung101]

Hi, I updated the test code to include examples for the missing queries. The code that I was testing is a fixed point divider that comes from this blog. I'm pretty sure that this code is permissively licenced, but in case that's an issue, I may have some time to rewrite an equivalent test myself.

Also to note, I only updated the examples in the SystemVerilog test file, because both the test module and the Treesitter grammar itself target SystemVerilog. Supporting Verilog is more of a side effect, as I believe that Verilog is more or less a subset of SV.

The last thing I did was also add some additional queries for a few parentheses I noticed I was missing. Hopefully I didn't miss any of them in the test file! Also, I fixed the incorrect @begin/@end queries which makes highlighting brackets in expressions behave correctly.

[HiPhish]

Merged, thank you very much.