HigashiKed
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3 years ago A new and improved semiconductor memory device incorporating a coupling capacitor between two CMOS inverters to immunize the circuit from radiation interference without the known disadvantages of resistive hardened memory device. This invention relates in general to an improved random access memory and in particular to a static random access memory with an improved technique for immunizing the memory to single event upsets due to an ionizing radiation hit. While static RAMs are less sensitive to single event upsets, such as ion penetration, than are dynamic RAMs, the data in conventional static RAM circuits without any immunity or radiation hardness can be destroyed in the event of ion penetration. This is because certain radiation impulses can cause the RAM memory latch to make unplanned state changes from which the circuit is unable to recover once the radiation is no longer present. The most well known prior art technique or method for immunizing a static RAM against such single event ion penetrations is by incorporating decoupling resistors between the two storage nodes. With this method the storage nodes are isolated until the RAM latch has had an opportunity to recover its logic state prior to the ion radiation hit. However, with this decoupling resistor technique there are usually extra process steps and masks required. The entire response time of the circuit is also increased since the write cycle must be extended. Resistance slows the transition time so that the latch cannot be written accidentally by an ionizing pulse. Thus, this method is time dependent. With this technique a finite delay, say 5 ns, must be added to the feedback loop of the latch to prevent single event upsets. To deliberately write resistively hardened latches by normal means, thus requires an electrical pulse width of a longer duration, say at least 10 ns, thereby extending or increasing the normal response time of the circuit. Also, where resistors are put into the memory cell to harden the circuit to radiation impulses, the resistors have been found to create additional problems due to the large variation in their value. It is difficult to control the actual value of a resistor because of its sensitivity to temperature and because of variations in the processing of the resistors, i.e., doping levels, line widths, etc. However, while resistive hardened circuits may impose certain restraints on the memory circuit, such as an upper limit of approximately 50-100 MHz on the frequency of the latch operation, this technique of employing the resistors does not appreciably increase the circuit real estate or area. Such a feature is desirable in fabricating memory devices. Therefore, prior to the present invention, the decoupling resistor technique was the best technique known for immunizing a RAM to single event upsets. On the other hand, it is desirable to have a memory device which is immune to single event upsets but which does not have the drawbacks associated with the memory devices incorporating decoupling resistors. That is, it is desirable to have a memory device which gives all of the benefits of decoupling resistors but which does not make use of the resistors. Consequently, it is desirable to have a static random access memory device which is immune to the single event upsets such as ionizing radiation pulses but where the efficiency and response time of the circuit are not compromised. It is also desirable to have an improved memory device which is immune to radiation interference but which does not appreciably increase the area or size of the circuit. The broadest aspect of the present invention is defined in claim 1. In view of the commonly known problems which still exist with respect to static random access memories which are not sufficiently immune to single event upsets and which must incorporate decoupling resistors in order to immunize the circuit to radiation interference and the other known disadvantages of resistive hardened memory devices, it is clear that there is a need in the semiconductor industry for a static random access memory with radiation hardness which accomplishes the objects defined above. According to the invention semiconductor memory device which incorporates a coupling capacitor between the two storage nodes to achieve radiation hardness of the circuit. The invention eliminates the undesirable side effects of resistive hardening such as the increased response time of the circuit. The invention also make permits to use of a capacitor which is more stable over process variations and temperature variations than are resistors. Furthermore, the capacitor does not require any additional die area. The invention as set forth in Figure 3 provides for a more desirable alternative to the resistive hardening technique against radiation interference. As in both of the prior art memory devices discussed above, the memory device is only vulnerable when a single event ion or outside radiation interference hits the storage node when the node is in the logic \"1\" state. That is, if a single event ion or radiation interference should hit a data storage node N₁ in the logic \"0\" state, there will be no detrimental effect on the circuit. Assuming a single event ion hit on storage node N₁, the transition of N₁ from an original logic state of \"1\" at Vcc to a new logic state of \"0\" at 0V occurs. Simultaneously, due to the capacitor coupling effect, the voltage on storage node N₂ will also change and will be driven down from OV to a negative voltage value approaching -Vcc. Now the voltage across both nodes N₁ and N₂ is dropping in the same direction with the voltage across N₁ fast approaching 0 while the voltage across N₂ fast approaching -Vcc. This voltage drop across nodes N₁ and N₂ is illustrated in Fig. 3A. As is further illustrated in Fig. 3A, the voltages across N₁ and N₂ will never be equal as occurs for the prior art circuits illustrated at the crossover points in Figs. 1A and 2A. This lack of a crossover point of the voltages across N₁ and N₂ makes the circuit of Fig. 3 immune to single event upsets. In practice, the voltage drop at N₂ is limited by the P-N diode clamping between the transistor drain and the substrate or well. This clamps the voltage at N₂ to approximately one diode voltage drop below ground. At this point, both sides of the CMOS latch have a logic \"0\" input even though the two stages (inverters A and B) are being driven by different voltages. This is an unstable condition for the latch and both stages of the latch will initially attempt to drive high. However, because the output of node N₂ is approximately one diode drop lower than the output of N₁ the inherent voltage gain of the cross-coupled latch will drive these nodes to their correct levels assuming the latch has been properly designed and balanced, i.e. N₁ will achieve its original logic state of \"1\" before N₂ is able to go high. AsN₁ achieves a logic state of \"1\", it will drive N₂ back to its logic state of \"0\" and the inverters will both resume their logic states prior to the radiation interference. While the invention has been described with specific applications primarily directed to radiation hardening for static RAMs, it is anticipated that the invention may also be applied to the hardening of latches in general, e.g., storage registers, shift registers, counters, etc. Furthermore, the invention may have applications outside of the area of radiation hardening. For example, the invention may be used to improve the immunity of a memory cell to power supply glitches for poly-load-resistor RAMs. This increased stability will become critically important as memory cells shrink in size with each generation of technology advancement. Also, while the invention has been described with specific application to static RAM designed for CMOS process technology it is anticipated to have application for other process technologies, e.g., NMOS, Bipolar, etc. 1. In a semiconductor memory device of the type having a plurality of transistor means (T₁ - T₆), each of said transistor means having a source, drain and a gate and wherein each of said transistors is electrically connected to the adjacent transistor and the drains of at least two adjacent transistors are coupled with a capacitive means.(Cc). 2. In a semiconductor memory device of the type having a plurality of transistor means (T₁ -T₆), each of said transistor means having a source, drain and a gate, with the gates of the first and second transistor means being connected to the drains of the third and fourth transistor means, and with the gates of the third and fourth transistor means being coupled to the drains of the first and second transistor means, wherein the improvement comprises capacitive means for coupling the drain of one of said transistor means (Cc)to the drain of another one of said transistor means. 3. In a semiconductor memory device of the type having a plurality of transistor means, each of said transistor means having a source, drain and gate, with the drain of the first (T₁) of said transistor means being connected to the drain of the second (T₂) transistor means and the drain of the third (T₃) transistor means being connected to the drain of the fourth transistor means and with the drain of the third transistor means being connected to the gates of the first and second transistor means and the drain of the first transistor means being connected to the gates of the third and fourth transistor means, wherein the improvement comprises capacitive means (Cc) for coupling the drains of the first (T₁) and second (T₂) transistor means to the drains of the third (T₃) and fourth (T₄) transistor means.
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