search

HoneyGol-Microsystems / vesp-alpha

RISC-V based student processor for embedded applications.
GNU General Public License v3.0
3 stars 0 forks source link

Add variable-stage synchronizer #27

Closed andreondra closed 1 year ago

andreondra commented 1 year ago

CLK-domain synchronization should occur on ALL inputs to avoid metastability. Simple 2 stage FF synchronizer should help but the module should be parametrized.