HoneyGol-Microsystems / vesp-alpha

RISC-V based student processor for embedded applications.
GNU General Public License v3.0
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Remove `r0` register #78

Closed medexs closed 1 year ago

medexs commented 1 year ago

The r0 register is hardwired to zero and thus not used in the Verilog code, so there is no need to declare it in the register file.