search

IAIK / memsec

Framework for building transparent memory encryption and authentication solutions
GNU General Public License v3.0
25 stars 10 forks source link

testing on ZedBoard #1

Closed m1karmida closed 2 years ago

m1karmida commented 2 years ago

Hi, i want to ask you some information about testing phase. I read your paper and i hunderstood that you've used different benchmarks on top of the linux Kernel. In this case, linux Kernel needs of the device tree generated from the exported xsa file of the block design. Before the device tree compilation, there are some patches to apply on the dtsi files or it's already correct in this way?

Thank you for the answer.

niosHD commented 2 years ago

Hi! It already has been some time since I worked on this topic but as far as I remember you don't necessarily need any device tree from the Xilinx tools in this case. Changing the base address and size of where the RAM is for the kernel to the FPGA within the SoC (which implements memory encryption transparently) should suffice. I guess you can do that via the device tree or probably also via the kernel command line.