search

IBM / AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Apache License 2.0
400 stars 101 forks source link

[close #4] add function simulation file. #5

Closed Junsong-Wang closed 5 years ago

Junsong-Wang commented 5 years ago

Signed-off-by: JUN SONG WANG junsongw@cn.ibm.com