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IBM / AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
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vsim simulation failing #6

Closed Mutinifni closed 5 years ago

Mutinifni commented 5 years ago

Environment

OS: Ubuntu 16.04 Kernel: 4.15.0-47-generic Caffe version: https://github.com/BVLC/caffe rc3 Python version: 2.7.11+ AccDNN version: git commit with 8f0ec8e Vivado version: 2018.2

Problem

I am attempting to run the simulation framework (SIMULATION_ONLY=True in settings.py) for CIFAR-10, as described in the README. I with a different Xilinx device part, specifically xc7z010iclg225-1L instead of the default xc7vx690tffg1157-2; however this compiles just fine with around 88% utilization.

I proceeded to the vsim infrastructure and have compiled the model using comp_model after sourcing sim_model.tcl. However, when I attempt to sim, I face the following error:

[....]
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/blk_mem_gen_v8_4_1.blk_mem_gen_v8_4_1_mem_module
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/blk_mem_gen_v8_4_1.blk_mem_gen_v8_4_1_output_stage
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/blk_mem_gen_v8_4_1.blk_mem_gen_v8_4_1_softecc_output_reg_stage
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/blk_mem_gen_v8_4_1.blk_mem_axi_regs_fwd_v8_4
# Loading work.bit_trunc
# Loading work.multiplier
# Loading work.acc_addr
# Loading work.mul16x16_signed
# Loading work.mul16x16_signedmult_gen_v12_0__parameterized0
# Loading work.mul16x16_signedmult_gen_v12_0_viv__parameterized0
# Loading work.addr4
# Loading work.addr2
# ** Warning: (vsim-3008) ./model_tb.v(445): [CNNODP] - Component name (u0_cls_conv1_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(445): Unresolved reference to 'u0_cls_conv1_layer' in u0_module.u0_cls_conv1_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(461): [CNNODP] - Component name (u0_cls_conv2_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(461): Unresolved reference to 'u0_cls_conv2_layer' in u0_module.u0_cls_conv2_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(477): [CNNODP] - Component name (u0_cls_conv3_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(477): Unresolved reference to 'u0_cls_conv3_layer' in u0_module.u0_cls_conv3_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(493): [CNNODP] - Component name (u0_cls_ip1_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(493): Unresolved reference to 'u0_cls_ip1_layer' in u0_module.u0_cls_ip1_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(501): [CNNODP] - Component name (u0_cls_ip2_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(501): Unresolved reference to 'u0_cls_ip2_layer' in u0_module.u0_cls_ip2_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(453): [CNNODP] - Component name (u0_cls_pool1_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(453): Unresolved reference to 'u0_cls_pool1_layer' in u0_module.u0_cls_pool1_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(469): [CNNODP] - Component name (u0_cls_pool2_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(469): Unresolved reference to 'u0_cls_pool2_layer' in u0_module.u0_cls_pool2_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3008) ./model_tb.v(485): [CNNODP] - Component name (u0_cls_pool3_layer) is not on a downward path.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Error: (vsim-3043) ./model_tb.v(485): Unresolved reference to 'u0_cls_pool3_layer' in u0_module.u0_cls_pool3_layer.
#    Time: 0 ps  Iteration: 0  Instance: /model_tb File: ./model_tb.v
# ** Warning: (vsim-3015) ./model_tb.v(112): [PCDPC] - Port size (512) does not match connection size (64) for port 'blob_din'. The port definition is at: ../src/model.v(55).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module File: ../src/model.v
# ** Warning: (vsim-3015) ./model_tb.v(112): [PCDPC] - Port size (512) does not match connection size (64) for port 'blob_dout'. The port definition is at: ../src/model.v(48).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module File: ../src/model.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(528): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv1_layer/u_controller/u_mul16_unsigned_1 File: ../src/mul16_unsigned_funcsim.v
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/unisims_ver.x_lut1_mux2
# ** Warning: (vsim-3015) ../src/controller_v2.v(535): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv1_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(542): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv1_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(583): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv1_layer/u_controller/u_mul16_unsigned_6 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(827): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv1_layer/u_controller/u_mul16_unsigned_4 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(834): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv1_layer/u_controller/u_mul16_unsigned_5 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2_a.v(431): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_pool1_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2_a.v(438): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_pool1_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(528): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv2_layer/u_controller/u_mul16_unsigned_1 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(535): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv2_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(542): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv2_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(583): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv2_layer/u_controller/u_mul16_unsigned_6 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(827): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv2_layer/u_controller/u_mul16_unsigned_4 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(834): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv2_layer/u_controller/u_mul16_unsigned_5 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2_a.v(431): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_pool2_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2_a.v(438): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_pool2_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(528): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv3_layer/u_controller/u_mul16_unsigned_1 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(535): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv3_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(542): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv3_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(583): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv3_layer/u_controller/u_mul16_unsigned_6 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(827): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv3_layer/u_controller/u_mul16_unsigned_4 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(834): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_conv3_layer/u_controller/u_mul16_unsigned_5 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2_a.v(431): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_pool3_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2_a.v(438): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_pool3_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(528): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip1_layer/u_controller/u_mul16_unsigned_1 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(535): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip1_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(542): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip1_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(583): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip1_layer/u_controller/u_mul16_unsigned_6 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(827): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip1_layer/u_controller/u_mul16_unsigned_4 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(834): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip1_layer/u_controller/u_mul16_unsigned_5 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(528): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip2_layer/u_controller/u_mul16_unsigned_1 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(535): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip2_layer/u_controller/u_mul16_unsigned_2 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(542): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip2_layer/u_controller/u_mul16_unsigned_3 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(583): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip2_layer/u_controller/u_mul16_unsigned_6 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(827): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip2_layer/u_controller/u_mul16_unsigned_4 File: ../src/mul16_unsigned_funcsim.v
# ** Warning: (vsim-3015) ../src/controller_v2.v(834): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /model_tb/u0_module/u0_ip2_layer/u_controller/u_mul16_unsigned_5 File: ../src/mul16_unsigned_funcsim.v
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/unisims_ver.x_lut2_mux4
# Loading /scratch/pratyush/intelFPGA/19.1/modelsim_ase/xilinx/unisims_ver.x_lut3_mux8
# Error loading design
# End time: 14:50:56 on Oct 10,2019, Elapsed time: 0:00:01
# Errors: 8, Warnings: 46
# No Design Loaded!

Am I missing something?

Mutinifni commented 5 years ago

Thanks! that works, and I'm able to simulate it in steps (up to simulation breakpoints). However, if I run to finish, vcs always crashes without any output. Do you also encounter this? The simulation data is not generated post crash.

This might simply be because I'm using a free edition of vsim, but I wanted to make sure.

Junsong-Wang commented 5 years ago

I am using modelsim instead of vcs, I am afraid I can not help you on this tool issue.

Mutinifni commented 5 years ago

Sorry, I actually meant I am using the free version of Intel / Altera ModelSim (vsim), not vcs.

Edit: note that this is the same one as mentioned on step 5 of the README (https://github.com/IBM/AccDNN#simulation-without-involing-hardware)

Junsong-Wang commented 5 years ago

I see. By default, the testbench data and output data will be saved to sim/data, do you manually create a directory in sim/data?

Other try is to add fflush after each fdisplay in model_tb.v file to make sure all the output data will be flushed to disk immediately.

Mutinifni commented 5 years ago

Yes, I did create the folder in the previous run. However, I just noticed in the transcript that one of the errors is that it cannot find weights_sim.dat in that folder. So I copied this from /build/coe/ and it still fails with other errors, a sampling of which are listed below. Thanks!

# ** Warning: (vsim-3015) ../src/controller_v2.v(528): [PCDPC] - Port size (16) does not match connection size (32) for port 'B'. The port definition is at: ../src/mul16_unsigned_funcsim.v(21).
[...]
# **0 Error: (vish-4014) No objects found matching '/model_tb/u0_module/u0_conv2_layer/u_vector_muladd_0_0/gen_adder_8b/a2_tmp_0'.
# Error in macro ./../wave/cifar10.do line 51
# (vish-4014) No objects found matching '/model_tb/u0_module/u0_conv2_layer/u_vector_muladd_0_0/gen_adder_8b/a2_tmp_0'.
#     while executing
# "add wave -noupdate -format Literal /model_tb/u0_module/u0_conv2_layer/u_vector_muladd_0_0/gen_adder_8b/a2_tmp_0"
# ** Warning: (vsim-3116) Problem reading symbols from linux-gate.so.1 : can not open ELF file.
# Block Memory Generator module model_tb.u0_module.u0_conv1_layer.u_conv1_rm_ram_0.inst.native_mem_module.blk_mem_gen_v8_4_1_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
# Block Memory Generator module model_tb.u0_module.u0_conv1_layer.u_conv1_wm_ram.inst.native_mem_module.blk_mem_gen_v8_4_1_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
[...]
# Block Memory Generator module model_tb.u0_module.u0_ip2_layer.u_ip2_bm_ram.inst.native_mem_module.blk_mem_gen_v8_4_1_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
# DRC Error : Reset is unsuccessful at time              1237600.  RST must be held high for at least five WRCLK clock cycles, and WREN must be low before RST becomes active high, and WREN remains low during this reset cycle.
Junsong-Wang commented 5 years ago

It seems some signals are not found in the this case, these signals are used to observe the wave only, and may be different according to you model. You can remove or add any signals according to your debug purpose. I merged a pull request that removes all the unnecessary signals for avoiding any error and confuse.