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IHP-GmbH / IHP-Open-PDK

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
Apache License 2.0
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sg13g2_io: verilog: Add more cells #105

Closed dnltz closed 3 weeks ago

dnltz commented 3 weeks ago

All IO cells, even simple Filler cells, have to be defined for chip-level simulations. Add more dummy cells for Corner and Filler cells.

dnltz commented 3 weeks ago

@KrzysztofHerman figured out even more cells are required for chip-level simulations.

KrzysztofHerman commented 3 weeks ago

Thank you for contribution, it will be added in the PR #104