UDP and SDF forbids post-synthesis simulation with either Icarus Verilog or Verilator

[MaxenceBouvier]

Hi,

I am trying to simulate a post-synthesis design using either Verilator or icarus verilog (iVerilog) tools.

The design has been synthesized with YOSYS simulator and in the end instantiates some sg13g2_dfrbp_1 cells.

Unfortunately, the behavioral model of these cells rely on:

• User Defined Primitives (UDP) description.

• Standard Delay Format (SDF) timing definitions.

  So, I do not succeed running a simulation for the following reasons:

• SDF is not supported by Icarus Verilog. (here)
• UDP is not supported by Verilator. (here)

What do you recommend as a solution, apart from redefining the behavior of sg13g2_dfrbp_1 as simple D Flip Flops?

Thanks for your help.

[KrzysztofHerman]

Hi @MaxenceBouvier thank you for commenting on that. Please take a look at the OpenROAD-flow-scripts and our platform, namely ihp-sg13g2, available there. In short the technology mapping is done by Yosys using cell definition included in *.lib file.

[mole99]

I would like to add that SDF is partially supported by Icarus Verilog. I did some tests here with Sky130A: https://github.com/mole99/interconnect-tests Unfortunately, no timing checks are implemented yet.

Simulating at gate level without timing information should be no problem with Icarus Verilog. I just read the file sg13g2_stdcell.v without errors, there are of course warnings indicating the missing timing checks.

Make sure you are using a current version of Icarus Verilog.

[Blebowski]

Hi,

there is a VHDL simulator where the author started to integrate Verilog support. I have started to work on SDF annotation last summer, but the work is stalled for now. https://github.com/nickg/nvc/pull/757

It is not where you need it yet, but it is slowly moving there.

[MaxenceBouvier]

Thank you all for yours answers!

Hi @MaxenceBouvier thank you for commenting on that. Please take a look at the OpenROAD-flow-scripts and our platform, namely ihp-sg13g2, available there. In short the technology mapping is done by Yosys using cell definition included in *.lib file.

Thanks @KrzysztofHerman, indeed, I am able to synthesize and techmap, my design with the YOSYS synthesizer, however I do not succeed simulating the post-synthesis design.

I would like to add that SDF is partially supported by Icarus Verilog. I did some tests here with Sky130A: https://github.com/mole99/interconnect-tests Unfortunately, no timing checks are implemented yet.

Simulating at gate level without timing information should be no problem with Icarus Verilog. I just read the file sg13g2_stdcell.v without errors, there are of course warnings indicating the missing timing checks.

Make sure you are using a current version of Icarus Verilog.

With Icarus Verilog, the sg13g2_stdcell.v file can indeed be read, however the internal register behavior (for instance of sg13g2_dfrbp_1) is not correctly interpreted as it relies on the delayed_CLK and delayed_D signals. These signals are generated from a timing checks ($setuphold) and are thus not driven by the simulator.

[...]/ihp130/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v:459: warning: Timing checks are not supported and delayed signal "delayed_CLK" will not be driven.

Content of sg13g2_stdcell:l459:

$setuphold (posedge CLK, posedge D, 0, 0, notifier,,, delayed_CLK, delayed_D);

As a result, the signal are constantly set to x and post-synthesis simulation are not possible. @mole99 do you know if there is a way to tell Icarus Verilog to ignore the timing checks and drive the output signal as original the source? If not, it would be nice to have an alternative "pure" RTL description (no timing) of the IHP130 standard for quick functional verification of synthesized netlist.

[Blebowski]

@MaxenceBouvier would it be OK to add ifdef FUNCTIONAL to conditionally compile without timing checks ?

module sg13g2_a21oi_1 (Y, A1, A2, B1);
    output Y;
    input A1, A2, B1;

    // Function
    wire int_fwire_0, int_fwire_1;

    and (int_fwire_0, A1, A2);
    or (int_fwire_1, int_fwire_0, B1);
    not (Y, int_fwire_1);

`ifdef FUNCTIONAL
    // Timing
    specify
        (A1 => Y) = 0;
        (A2 => Y) = 0;
        if (A1 == 1'b1 & A2 == 1'b0)
            (B1 => Y) = 0;
        if (A1 == 1'b0 & A2 == 1'b1)
            (B1 => Y) = 0;
        if (A1 == 1'b0 & A2 == 1'b0)
            (B1 => Y) = 0;
        ifnone (B1 => Y) = 0;
    endspecify
`endif
endmodule
`endcelldefine

[mole99]

@MaxenceBouvier You must be using an older version of Icarus Verilog, in the latest version these signals are driven (but not delayed), which should be enough for a GL simulation :) Can you send me your version string?