Closed olisnr closed 1 day ago
for LVS the netlist format is CDL (Circuit Design Language), not SPICE:
.SUBCKT sg13g2_inv_1 A VDD VSS Y
*.PININFO A:I Y:O VDD:B VSS:B
MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
MX0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
.ENDS
so, while you can run the cross-check with the SPICE netlist as a schematic representation of the circuit, you'll have to do some preprocessing
via KLayouts LVS Options
dialog You can select *.cdl
, *.spice
and *.cir
. maybe somebody should change the text Netlist Path
to CDL-Netlist Path
?
and update the documentation:
https://ihp-open-pdk-docu.readthedocs.io/en/latest/verification/lvs/05_04_usage.html
when i have a .GDS and a .CDL with the same top-level-ports, shouldnt LVS handle the ports with the same name as the same?
i get this:
@olisnr That might be because an issue in the design. It's how klayout is functioning.
Hi @olisnr, could you please upload this testcase?
@sergeiandreyev yes: ota_gds_netlist.zip
I've made a quick review of the netlist, and checked the LVS on the testcase with commercial flow as well - the LVS is not clean (property, nets, instances, connectivity errors), but there are no top-level port related violations
I would expect however 'out <-> op' violation to show-up)
you have to follow the required syntax (f.e. device parameters are missing from the .spice
file), also you have to check devices (cmim are missing from netlist)
what I do not understand is why I have all netlist ports in Database browser in capital letters, while in the netlist file I have ip in out sink
:
also, as you see, port names in layout are not consistent with your screenshot 3 days ago
@sergeiandreyev yes i used on older version of the .gds
in the .zip
, and it has the the output label still wrong.
i also tried to change all label in the .gds
and .spice
to uppercase, and i even tried to change the pin-order of the .spice
to the order of the TOP_extracted.cir
from the LVS-script, but it didnt change anything...
it seems there was a problem with the spice netlist. now it looks better i have no idea at the moment, why.
it seems that the LVS script only looks for M-devices (spice MOSFETs). but if i understand it correct the spice-models are X-devices (sub-circuits (XM with the use-spice-prefix option in Xschem)).
should this be changed? or documented?
the other thing is that the LVS seems not to accept spice parameters. will this be implemented? or is it be possible to ignore optional {} values?