Open vkrahul77 opened 2 months ago
it seems to be an issue in both nmos
and pmos
cells - there should be no any '.lbl' or '.bnd' GatPoly
layers, only '.drw' and '.pin'..
Thank you for finding!
Along with the posted bug, I noticed that there are a few DRC errors in NMOS-Cell. Here is a list: Min and Max size of contact should be 0.16 --> Cell has 0.14 Min Contact space should be 0.18 --> Cell has 0.16 Min Metal1 space or notch should be 0.18 --> Cell has 0.13
@vkrahul77 , I believe all these issues are fixed in the latest OpenPDK dev
branch:
In the "IHP Pycells", For Gate The PMOS has "GatPloy.lbl" while NMOS has "Gatpoly.drw" as shown:
Also, I've noticed a discrepancy in dimension input between NMOS and PMOS transistors within the tool. Specifically, while "1u" notation is accepted for PMOS, it's not permitted for NMOS. Instead, we're required to use scientific notation such as "1e-6".