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iob-axi
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Update V_AXI submodule
#21
arturum1
closed
1 year ago
0
fix(python): Fix python script shebang
#20
P-Miranda
closed
2 years ago
0
remove compilation warning
#19
JDLopes
closed
2 years ago
0
update V_AXI submodule
#18
JDLopes
closed
2 years ago
0
update V_AXI submodule
#17
JDLopes
closed
2 years ago
0
fix iob2axil and axil2iob modules
#16
JDLopes
closed
2 years ago
0
rename axil_port.vh file in iob2axil module
#15
JDLopes
closed
2 years ago
0
Update V_AXI submodule.
#14
PedroAntunes178
closed
2 years ago
0
update LIB and MEM submodules; update sources according new version of submodules
#13
JDLopes
closed
2 years ago
0
update LIB and MEM submodules; update sources according new version of submodules; fix axi_gen.py script to support parameters on aw and dw arguments
#12
JDLopes
closed
2 years ago
0
fix axi_gen.py script
#11
JDLopes
closed
2 years ago
0
add LIB submodule; rewrite iob2axi and its testbench; bugs fix; create a .gitignore file; merge with iob-axi/main; update sources; improve axi_gen.py script
#10
JDLopes
closed
2 years ago
0
bug fixes
#9
JDLopes
closed
2 years ago
0
rewrite iob2axil and axil2iob modules to avoid signal loops when both cores are connected to each other
#8
JDLopes
closed
2 years ago
0
change all reset signals to asynchronous in iob2axil module; add run signal to Control I/F; start to change the testbench; add MEM submodule; add FIFO to iob2axi module
#7
JDLopes
closed
2 years ago
0
iob2axil + axil2iob adapters: iverilog simulation gets stuck
#6
P-Miranda
opened
2 years ago
1
feat(intercon): Add axi interconnect hardware.mk
#5
P-Miranda
closed
2 years ago
0
update Makefile; add missing include in hardware.mk file from iob2axil module
#4
JDLopes
closed
2 years ago
0
fix hardware.mk for axil2iob module
#3
JDLopes
closed
2 years ago
0
update source paths; move Makefile to root directory; add AXI_MEM submodule
#2
JDLopes
closed
2 years ago
0
add first files
#1
JDLopes
closed
2 years ago
0