IObundle / iob-cache

Verilog Configurable Cache
MIT License
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Initial verilator simulation #104

Closed zettasticks closed 2 years ago

zettasticks commented 2 years ago

Go to hardware/simulation/verilator and do "make all" to do the simulation.

There are errors but those occur from the MEM submodule. I removed them to run the test but of course someone else should fix them.

With the errors removed, the simulation runs and produces a vcd file, called vcd.vcd.

Extra files are generated and can be cleaned by doing "make clean".

Important note: The reason that on the Makefile lines 14 and 15 are there is because the Verilator include is really picky with the spaces between the incdir (-I) and the path. For example, if I have a path that is /dir/, I cannot do "-I /dir/", because of the extra space, I have to do "-I/dir/".