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IObundle / iob-cache

Verilog Configurable Cache
MIT License
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`make doc-build-all` does not work #155

Closed dbrumley closed 2 years ago

dbrumley commented 2 years ago

The README says to run make doc-build-all. I consistently get an error about a missing settings64.sh file.

make doc-build DOC=pb;  make doc-build DOC=ug;
make[1]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make fpga-build FPGA_FAMILY=CYCLONEV-GT;  make fpga-build FPGA_FAMILY=XCKU;
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/quartus/CYCLONEV-GT build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "5CGTFD9E5F35C7"
../build.sh: line 5: /nios2eds/nios2_command_shell.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache_0.qxp] Error 127
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/vivado/XCKU build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "xcku040-fbva676-1-c"
../build.sh: line 3: /settings64.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache.edif] Error 1
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[1]: *** [Makefile:31: fpga-build-all] Error 2
make[1]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[1]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make fpga-build FPGA_FAMILY=CYCLONEV-GT;  make fpga-build FPGA_FAMILY=XCKU;
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/quartus/CYCLONEV-GT build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "5CGTFD9E5F35C7"
../build.sh: line 5: /nios2eds/nios2_command_shell.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache_0.qxp] Error 127
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/vivado/XCKU build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "xcku040-fbva676-1-c"
../build.sh: line 3: /settings64.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache.edif] Error 1
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[1]: *** [Makefile:31: fpga-build-all] Error 2
make[1]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make: *** [Makefile:51: doc-build-all] Error 2
jjts commented 2 years ago

We are working on it and should release it soon since the interest is rising. Sorry for the inconvenience and thanks for the interest. Meanwhile, if you have any specific questions to get you going, we'll be glad to answer. The code is stable and you should be able to use it once you understand its interface signals.

dbrumley commented 2 years ago

Thanks for the quick ack. I don't have a specific question. I'm trying to debug an issue for a client, and we're using verilator. I'm trying to figure out how rdata would ever be set given a sequence of wdata's. I hope that makes sense.

jjts commented 2 years ago

rdata is a front-end (facing the CPU) signal, meaning the CPU receives data from the cache using it.

wdata is another front-end for writing to the cache.

The CPU is either reading or writing, not both.

For reading one word from the cache, have the address ready and assert valid during one cycle.

If the ready signal is high in the next cycle, rdata has the requested word; you may immediately (combinatorially) de-assert the valid signal if you do not need to read another word. Or you can keep reading words in pipeline by keeping valid high and changing the address every cycle.

If the data is not in the cache, ready will not be asserted in the next cycle. Then hold the valid and address signals until ready is high; meanwhile, the word is read from the external memory (back-end) and placed in the cache.

To write, the process is similar. ready high in the next cycle means the word has been written to the cache; ready low means you need to wait with valid high and the same address until ready is high again; meanwhile, the data is written to the back-end.

As long as the data is in the cache, consecutive (pipelined) reads and writes are supported, one word per clock cycle.

I hope this helps.

jjts commented 2 years ago

documentation can now be generated on branch build-dir

dbrumley commented 2 years ago

TY! :) 👍 🥇

dbrumley commented 2 years ago

FYI: We have a blog post on fuzzing iob-cache to check coverage. Joint work with Micron. I've not seen much in fuzzing verilog, and it may be of interest. There is no expectation of finding vulnerabilities. However, it can radicallyi reduce the cost of building tests that cover nodes and edges in your design.

https://forallsecure.com/blog/running-iob-cache-in-mayhem

jjts commented 2 years ago

Hi David, Thanks, I saw your blog post -- very interesting

In fact, you may find vulnerabilities :-) ...