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IObundle / iob-cache

Verilog Configurable Cache
MIT License
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Understanding the flow of iob-cache #175

Closed krritd23 closed 2 years ago

krritd23 commented 2 years ago

Hello Community Is there any user documentation which explains basic flow of the "iob-cache" and how can we understand it.? I am getting perplexed with files getting generated after verilation in obj_dir directory. I am unable to generate user guide with the minimal commands provided. It is getting difficult in understand as a user, how the back-end ,front-end sections are in sync with main memory section and can they be tested from testbench Which sequence to follow for a basic successful test case

Thank you in advance.

jjts commented 2 years ago

We are adding a basic test to the verilator testbench. It should be ready in a couple of days.

This test writes to one memory address and then reads from the same address.

An external memory is missing from the verilator testbench. Of course a cache does not work without a memory attached.

As for the user guide it was working when I last tried though the document needs reviewing and is incomplete. Is it because of the FPGA compilation? You need to have vivado and quarts installed but it makes sense to disable that and not include implementation results by default.

krritd23 commented 2 years ago

I have tried make sim SIMULATOR=verilator simulating testbench by adding the below fewer changes. I wanted to see the output to analyse the changes But i dont even see the "clk" changes in gtkwave 20220523_173604 20220523_173713 Could you pleaee suggest in which manner i can configure such changes in testbench.cpp so as to to observe the gtkwave and can be understand Thank you in advance

codingUniv commented 2 years ago

Hello Please refer to the updated verilator testbench available on doc branch. It performs a simple write/read test. I hope it could help.

jjts commented 2 years ago

Documentation can now be generated on branch build-lib. Thanks.