IObundle / iob-cache

Verilog Configurable Cache
MIT License
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progress on simulation/test target #191

Closed codingUniv closed 2 years ago

jjts commented 2 years ago

This PR has no simulation content. Only makefiles but this is what I am doing. You can do simulation with the sources, a testbench and an improvised makefile or other script.

I expected you to add simulation test cases and try to work on those which are failing -- this is why I explained how the cache works . For example BE_IF=iob and write-back fails . Why? Any other test cases you want to add?

jjts commented 2 years ago

could not merge