iob-cache port addr width change (depending on CTRL_CACHE parameter)

IObundle / iob-cache

Verilog Configurable Cache

MIT License

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iob-cache port addr width change (depending on CTRL_CACHE parameter) #24

Closed joaovroque closed 4 years ago

jjts commented 4 years ago

You have to git pull before the PR: your hardware.mk is damaged which I fixed yesterday. Locally use CACHE_DIR and not ROOT-DIR, which is only for IOb-SoC. Change the repo to use CACHE_DIR.