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iob-cache
Verilog Configurable Cache
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feat(build-lib): Update iob_cache_setup.py; Remove makefile swreg.
#246
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arturum1
closed
1 year ago
arturum1
commented
1 year ago
Revert some changes from commit d8b13ab.
Generate headers directly in build dir.
Swreg is now handled by setup.py. There is no longer a need for it in hw_setup.mk and sw_setup.mk
Add macros
Change regs from string values to int
Manually add "clk_i" and "rst_i" signals, as included file contains "arst_i" that is not used by this component.