Add missing 'else' block in `iob_cache_control`

IObundle / iob-cache

Verilog Configurable Cache

MIT License

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Closed arturum1 closed 1 year ago

arturum1 commented 1 year ago

Add missing else block after the end of the if (USE_CTRL_CNT) begin block. Without this, quartus would throw an error about multiple writes to the rdata signal.
Fixed tab identation for ease of readability of Verilog blocks.

jjts commented 1 year ago

Why wqs this not happening on the master branch?

arturum1 commented 1 year ago

Why wqs this not happening on the master branch?

The master branch is correct. It has the 'else' block.